AI Silicon & Chiplets
Chiplets, UCIe, SerDes, DSPs, retimers, and the semiconductor foundation of AI infrastructure — how silicon choices shape system and network design.
102 video interviews · 2020–2026
Unified Network Fabric for Distributed AI Workloads Across Data Centers
- One unified fabric connects GPU resources across scale-up, scale-out, and scale-across layers
- Hardware-abstracted network OS runs across multiple silicon platforms
Full summary
For our Director's Cut, Sanjay Kumar, Vice President of Product Management and Marketing at Arrcus, and Keyur Patel, Founder and CTO at Arrcus, explain how Arrcus provides a unified network fabric that connects GPU resources across scale-up, scale-out, and scale-across layers for distributed AI workloads. They touch on how Arrcus differentiates itself through hardware-abstracted operating system software that works across multiple silicon platforms.
AI Networking at Scale: GPU Cluster Interconnect Solutions for Data Centers
- Nitro linear retimer driver extends active copper cables for GPU cluster interconnect
- Vesta 200 6.4T CPX optical engine targets cluster-scale optics
Full summary
Helen Xenos, Senior Director of Portfolio Marketing at Ciena, presents the company's innovations for GPU cluster interconnects including the Nitro linear retimer driver for active copper cables and the Vesta 200 6.4T CPX optical engine.
Big Outlook for XPU-Attach
- Marvell customizes every component in the XPU tray beyond the XPU itself
- CXL-enabled memory adds expansion and near-memory compute
- Security devices and high-performance NICs build on Marvell SerDes and IP platforms
Full summary
Will Chu, SVP and GM, Custom Cloud Solutions Business Unit at Marvell, discusses the company's expansion into XPU attach solutions, where Marvell customizes all components within the XPU tray beyond the XPU. The custom solutions include CXL-enabled memory for expansion and near-memory compute, security devices for AI infrastructure management, and high-performance NICs built on Marvell's SerDes and other IP platforms.
Linear Pluggable Optics for Data Center Efficiency
- 1.6T optical modules consume nearly double the power of 800G — up to +1kW on a 64-port switch
- Linear Pluggable Optics (LPO) cuts power by leaning on the switch ASIC's DSPs
Full summary
Neel Patel, GM of Optical Networking Component Solutions at Nokia, discusses the power consumption challenges of advancing optical modules in data centers, where 1.6T modules consume nearly double the power of 800G modules, potentially adding 1KW to a 64-port switch. He explains how Linear Pluggable Optics (LPO) addresses this by leveraging switch ASIC DSPs reducing power consumption.
Integration is the Real Race in AI Data Center Networking
- Hyperscaler AI demand is reshaping the data center networking market
- Integration — not any single component — is the real competitive race
- Nokia's portfolio spans switching silicon, DSPs, and Infinera-derived optics
Full summary
Mike Bushong, Vice President of Data Center at Nokia, discusses how AI workloads are fundamentally changing the data center networking market, with hyperscalers driving unprecedented demand and technical challenges. He explains that Nokia's broad portfolio across switching silicon, DSPs, and differentiated optics from the Infinera acquisition positions the company to handle complex integration challenges.
UALink 2.0: Open GPU Interconnect for AI Clusters
- UALink 2.0 released: protocol-physical separation, in-network compute, enhanced manageability
- Includes the consortium's first UCIe-based chiplet specification
- 115-member consortium expects customer solutions on 2.0 in 2027
Full summary
Kurtis Bowman, Chairman of the UALink Consortium, presents announces the release of UALink 2.0 specifications featuring protocol-physical layer separation, in-network compute capabilities, enhanced manageability, and the consortium's first UCIe-based chiplet specification, with the 115-member organization expecting customer solutions with 2.0 to be available in 2027.
UCIe Chiplet Connectivity for Performance & Efficiency
- UCIe connects chiplets in-package and package-to-package, including over co-packaged optics
- Bandwidth density is 1-4 orders of magnitude better than PCIe or Ethernet
- Enables composable systems with dynamic resource allocation
Full summary
Debendra Das Sharma, UCIe Consortium Chair at UCIe Consortium, explains how UCIe technology enables chiplet connectivity within packages and package-to-package connections using co-packaged optics for composable systems with dynamic resource allocation. UCIe delivers bandwidth densities with 1-4 orders of magnitude improvement over PCIe and Ethernet.
AI Data Centers Need Purpose-Built Networks
- AI workloads need deterministic, AI-specific networking rather than adapted general-purpose gear
- Upscale AI co-designs ASIC, systems, and software while maintaining openness
Full summary
In this director's cut video, Aravind Srikumar, SVP of Product at Upscale AI, presents the company's mission to deliver AI-specific networking solutions. Upscale AI differentiates through co-design optimization of ASIC, systems, and software to deliver deterministic performance for AI workloads while maintaining openness.
AI Data Centers Need Purpose-Built Networks
- AI workloads demand completely lossless, synchronized networks
- Purpose-built silicon, systems, and software for scale-up and scale-out — not adapted general-purpose infrastructure
Full summary
Aravind Srikumar, SVP, Product at Upscale AI, explains how AI workloads require completely lossless, synchronized networks. He shares how Upscale AI delivers AI-specific networking silicon, systems, and software purpose-built for both scale-up and scale-out environments, rather than adapting general-purpose infrastructure.
Building Service Provider Networks for the AI Era
- AI-era SP networks must handle high traffic volumes, latency-sensitive workloads, and traffic secured within sovereign boundaries
- Cisco positions its new Silicon 1 technology and routing systems as purpose-built for these AI-era demands
Full summary
Gurudatt Shenoy, Senior Vice President of Data Center and Provider Connectivity at Cisco Systems, discusses how AI requires service provider networks that can manage high traffic volumes, performance-sensitive workloads, and secure traffic within sovereign boundaries. He explains that Cisco addresses these requirements through its new Cisco Silicon 1 technology and routing infrastructure systems specifically designed for AI-era demands.
The New Open Centralized Unit Distributed Unit (OCUDU) Effort
- Wireless vendors are shifting to software differentiation atop standardized CPUs and GPUs
- Linux Foundation OCUDu and OCP projects open the door to hardware harmonization
- Marvell claims to be the only provider of macro-grade merchant silicon, trading custom silicon for better cost and power at scale
Full summary
Joel Brand, AVP, Product Marketing at Marvell, explains how major wireless vendors are shifting to software differentiation while adopting standardized CPUs and GPUs, creating opportunities for harmonization through initiatives like the Linux Foundation's OCUDu and OCP projects. He highlights that Marvell is uniquely positioned as the only provider of macro-grade merchant silicon to address the industry's economic challenges by moving from custom silicon to market-optimized solutions that offer better cost efficiency and power performance at scale.
Building at Scale: Ethernet & Optics
- Ethernet for Scale-Up Networking Group 1.0 spec expands racks from 64-128 XPUs to 1K XPUs
- Tomahawk 6 in volume production: first with 64 ports of 1.6Tbps, 200G SerDes and CPO
- New Jericho 4 enables cross-data center cluster deployment; Broadcom joins OCI MSA
Full summary
Hasan Siraj, VP of Product Management in the Core Switching Group at Broadcom, highlights the Ethernet for Scale-Up Networking Group's 1.0 specification and rack expansion from 64-128 XPUs to 1K XPUs. He also announces Tomahawk 6 shipping in volume production as the first to support 64 ports of 1.6Tbps with 200G SerDes and CPO, the company's participation in the OCI MSA, and the new Jericho 4 enabling cross-data center cluster deployment.
Broadcom's 400G/Lane Taurus Optical DSP
- Taurus is the industry's first 400 Gbps-per-lambda PAM4 optical DSP
- Enables low-cost, low-power 1.6T transceivers and a path to 3.2T transceivers
- Targets 200 terabit switch networking systems for AI infrastructure
Full summary
Gang Qiu, Product Line Manager, Marketing at Broadcom, presents Taurus, the industry's first 400 gigabit per lambda PAM4 optical DSP designed to help customers scale AI infrastructure at OFC 2026. The solution enables next-generation low-cost, low-power 1.6 terabit transceivers and paves the path to 3.2 terabit transceivers in 200 terabit switch networking systems.
Broadcom's 3.5D Silicon
- Broadcom's 3.5D silicon stacks two compute dies face-to-face on an interposer, beyond standard 2.5D
- First 3.5D product now shipping to Fujitsu
- Technology being adopted across all major XPU partners
Full summary
Harish Bharadwaj, VP of Marketing for the ASIC Product Division at Broadcom, discusses the company's 3.5D silicon technology that stacks two compute dies face-to-face on an interposer, advancing beyond the industry's standard 2.5D approach. Broadcom is now shipping its first 3.5D product to Fujitsu, with the technology being adopted across all major XPU partners.
GPU Cluster Connectivity
- Ciena Nitro linear retimer driver targets active copper cables for GPU cluster interconnects
- Vesta 200 is a 6.4T CPX optical engine for high-capacity AI networks
- Positioned as flexible, power-efficient connectivity options
Full summary
Helen Xenos, Senior Director of Portfolio Marketing at Ciena, presents the company's innovations for GPU cluster interconnects at OFC, including the Nitro linear retimer driver for active copper cables and the Vesta 200 6.4T CPX optical engine. These solutions provide flexible, power-efficient connectivity options to help customers build high-capacity networks for modern AI infrastructure.
Silicon Photonics OCS: 1000x Faster Switching
- iPronics silicon photonics OCS reconfigures 1000x faster than previous solutions
- 32-radix switch ramping in production; 64x64 port OCS chip already fabricated
- Establishing a Thailand production line, with plans to double radix annually
Full summary
Christian Dupont, CEO of iPronics, presents the company's silicon photonics-based optical circuit switches that achieve reconfiguration times a thousand times faster than previous solutions, enabling rapid network switching for improved reliability and performance in data centers. iPronics is establishing a production line in Thailand to meet volume demands, with their 32-radix switch currently ramping up in production and a 64x64 port OCS chip already fabricated, while planning to double radix annually to improve port density and integration.
Marvell's 800G Coherent Light Module
- Marvell demos the industry's first 800G coherent light module, powered by its Aquila DSP
- Optimized for O-band campus data center interconnects with links up to 20 km
- Demo shows strong pre-FEC performance and zero uncorrectable code words
Full summary
Vivek Thyagarajan, Application Engineer at Marvell, demonstrates the industry's first 800G coherent light module powered by Marvell's Aquila DSP, optimized for O-band campus data center interconnects with links up to 20 km. The demonstration shows excellent pre-FEC performance, a clear coherent constellation diagram, and zero uncorrectable code words, confirming clean link operation.
1.6T PAM4 TRO Electriccal
- Marvell demos a 1.6T PAM4 TRRO electrical system with RT DSP at 200 Gbps per lambda
- Delivers 21 dB output TCQ and 0.995 linearity with wide-open eye patterns
- Targets high-speed data center, AI networking, and switching fabric interconnects
Full summary
Rittik Shah, Senior Staff Application Engineer at Marvell, demonstrates a 1.6T PAM4 TRRO electrical system at OFC 2025, featuring RT DSP technology operating at 200 Gbps per lambda with 21 dB output TCQ and 0.995 linearity. The demonstration showcases wide open eye patterns designed for high-speed data center, AI networking, and switching fabric interconnect applications.
Silicon Photonics: Integrated Lasers & DWDM at Scale
- Scintil integrates indium phosphide lasers via a proprietary 'backside on box' silicon photonics process
- External light source combines lasers, muxes, photodiodes, and wavelength references on a single die for DWDM
- Evaluation kits ship to select customers in Q2; high-volume deployment expected by 2028
Full summary
Matt Crowley, CEO of Scintil Photonics, presents the company's heterogeneous silicon photonics technology that integrates indium phosphide lasers using a proprietary "backside on box" process. The company's external light sources combine lasers, muxes, photodiodes, and wavelength references on a single die to address AI data center demands for dense wavelength division multiplexing, with evaluation kits shipping to select customers in Q2 and high-volume deployment expected by 2028.
1.6Terabit Ethernet Demos
- 1.6 terabit Ethernet demonstrated using 200G-per-lane technology
- Multi-vendor demo includes Arista, Cisco, HPE, Keysight, and Teledyne LeCroy equipment
- Covers DSP-based, LPO, and LRO optical interconnect configurations
Full summary
Dave Estes, Hardware Engineer at VIAVI Solutions, presents demonstrations at the Ethernet Alliance booth at OFC 2025, showcasing the evolution toward 1.6 terabit Ethernet capabilities using 200G per lane technology with equipment from major vendors including Arista, Cisco, HPE, Keysight, Teledyne LeCroy, and others. The demonstrations feature various optical interconnects including DSP-based, LPO, and LRO configurations.
Optical Networks, AI Chip Design & Memory Architecture
- Hybrid electrical-optical connectivity evolves toward fully optical by 2027
- AI capabilities become more deeply integrated into chip design technologies
- Memory capacity expands beyond traditional HBM via attached or disaggregated architectures
Full summary
Noam Mizrahi, EVP and Corporate CTO at Marvell, presents three key predictions for the semiconductor and AI infrastructure landscape in the coming year. He anticipates hybrid electrical-optical connectivity evolving to fully optical by 2027, greater integration of AI capabilities into chip design technologies, and expanded memory capacity beyond traditional HBM through attached or disaggregated architectures.
Secure By Design with Zero-Trust Networking
- NetFoundry's Galeal Zino and AvidThink's Roy Chua explore zero-trust native networking during a self-driving demo.
- NetFoundry's software overlays enforce strong authentication for clients including top US banks and Fortune 500 companies.
Full summary
Galeal Zino, Founder and CEO of NetFoundry, and Roy Chua, Principal and Founder of AvidThink, explore NetFoundry's zero-trust native networking technology during a self-driving vehicle demonstration in San Francisco. The discussion highlights how NetFoundry enables secure global networks between various endpoints through software-based overlays that enforce strong authentication and authorization, serving major clients including top US banks and Fortune 500 companies.
Lightmatter on Breaking the AI Interconnect Bottleneck
- Lightmatter's Passage photonic technology boosts chip connectivity and bandwidth for AI.
- Uses silicon photonics for high-speed data transmission.
- L series is designed to integrate with existing data center infrastructure.
Full summary
Steve Klinger, VP Product at Lightmatter, showcases their Passage photonic technology that tackles AI computing bottlenecks by enhancing chip connectivity and bandwidth capabilities. The solution enables high-speed data transmission through silicon photonics and provides seamless integration with existing data center infrastructure through their L series offering.
Marvell on Custom HBM & SRAM for AI Chips
- Marvell's memory strategy centers on embedded SRAM IP, custom HBM, and the Striker aggregation device.
- Aims to improve bandwidth and reduce latency across multiple memory types.
Full summary
Mark Kuemerle, VP of Technology and CTO of ASIC Business Unit at Marvell, presented key memory optimization strategies at the AI Infrastructure Summit, focusing on embedded SRAM IP, custom HBM, and the Striker memory aggregation device. These innovations from Marvell enhance data center performance by improving bandwidth and reducing latency across multiple memory types.
Building Blocks for AI Processing
- Marvell's new die-to-die interface triples bandwidth density.
- Cuts power consumption by 40-70% versus prior approaches.
- IP block improves interconnect between dies and custom HBM.
Full summary
Mark Kuemerle, VP of Technology and CTO of ASIC Business Unit at Marvell, presented the company's new die-to-die interface technology at the AI Infrastructure Summit, highlighting its ability to triple bandwidth density while reducing power consumption by 40-70%. The innovative IP block enhances interconnect capabilities between dies and custom HBM, marking a major step forward in data center AI system development.
Xscape Photonics on Scaling AI with Light
- Xscape Photonics builds silicon photonics lasers to close AI bandwidth gaps.
- Adapts wavelength division multiplexing to generate multiple wavelengths on silicon chips.
- Initial products target AI fabric and accelerator vendors.
Full summary
Vivek Raghunathan, Co-Founder and CEO of Xscape Photonics, is developing silicon photonics-based laser solutions to address bandwidth constraints in AI computing systems, where GPU-to-memory bandwidth significantly outpaces package-to-package communication. The company's technology adapts wavelength division multiplexing to create scalable lasers generating multiple wavelengths on silicon chips, with initial products targeting AI fabric and accelerator vendors.
Use Cases for Chiplets in AI Clusters
- AI demand plus maturing die-to-die interface standards are the twin drivers accelerating chiplet adoption.
- Three chiplet use cases: compute-to-compute (high bandwidth, low latency), compute-to-IO for extended connectivity, and compute-to-optics.
- Compute-to-optical interfacing targets long-distance communication across AI clusters.
Full summary
Tony Chan Carusone, Chief Technology Officer at Alphawave Semi, discusses how AI demand and maturing die-to-die interface standards are accelerating chiplet adoption. He outlines three main applications: connecting compute chiplets with high bandwidth and low latency, linking compute cores to IO chiplets for extended connectivity, and interfacing compute chiplets with optical components for long-distance AI cluster communication.
Four Connectivity Fabric Innovations for AI Clusters
- Astera Labs spans four connectivity innovations: PCIe Gen 6, the Cosmos software suite, and Leo CXL smart memory controllers.
- CXL smart memory controllers position Astera in the memory-expansion layer of AI clusters.
- The company is positioning itself as a leader in UALink development.
Full summary
Paroma Sen, Vice President of Corporate Marketing at Astera Labs, showcases four major data center innovations including PCI Gen 6 solutions, Cosmos software suite, and Leo CXL smart memory controllers 5. She shares the company's expanding technology portfolio while highlighting their leadership in UALink development.
Breaking the AI Data Bottleneck
- Baya's Network on Chip (NoC) technology targets on-die data movement bottlenecks in AI compute architectures.
- Its chiplet-ready foundational product has already shipped to multiple customers.
- Baya is expanding beyond its core into automotive and data center markets.
Full summary
Sailesh Kumar, CEO of Baya Systems, leads the development of Network on Chip (NoC) technology that addresses data movement challenges in AI compute architectures. Baya has successfully delivered its chiplet-ready foundational product to multiple customers and is expanding into automotive and data center markets.
Speeding Forward with PCIe Gen 6 and 7
- Marvell demoed PCIe Gen 6 retimers and Gen 7 technology as critical enablers for scaling up AI infrastructure.
- A PCIe Gen 7 system hit 128G transfer speeds with improved bit error rates on TSMC's 3nm process.
- The Gen 6 demo used a three-board setup showcasing retimer capabilities.
Full summary
Annie Liao, Product Management Director at Marvell, presents PCIe Gen 6 retimer solutions and PCIe Gen 7 technology critical for scaling up AI infrastructure. The demonstrations include a three-board PCIe Gen 6 setup with retimer capabilities, and a PCIe Gen 7 system achieving 128G transfer speeds with improved bit error rates through TSMC's 3nm process.
Custom XPU Solutions: Memory, Security & Networking
- Marvell is expanding beyond the XPU to customize every component in the XPU tray as an attach-solutions play.
- CXL-enabled memory targets both capacity expansion and near-memory compute.
- Portfolio adds security devices for AI infrastructure management and high-performance NICs.
Full summary
Will Chu, SVP and GM, Custom Cloud Solutions BU, discusses the company's expansion into XPU attach solutions, where Marvell customizes all components within the XPU tray, including CXL-enabled memory for expansion and near-memory compute, security devices for AI infrastructure management, and high-performance NICs.
PCIe Evolution: From 5.0 Retimers to 8.0 Optical Solutions for AI
- Marvell's PCIe retimer roadmap spans generations 5.0 through 8.0.
- Electrical solutions face mounting challenges at 128 and 256 Gbps per lane, pushing toward optical PCIe.
- Optical strategy pairs module/cable partnerships with in-house co-packaged optics (CPO).
Full summary
Annie Liao, Product Management Director outlines Marvell's PCIe retimer product roadmap from generations 5.0 through 8.0, explaining how current electrical solutions will face increasing challenges at higher data rates of 128 and 256 Gbps per lane. She describes their strategic development of optical PCIe solutions, including partnerships for optical modules and cables as well as in-house co-packaged optics (CPO) technology.
Marvell's CPO Switch Demo
- Marvell's CPO reference platform is a liquid-cooled 1 OU system with 16 6.4T silicon-photonics light engines.
- Scaling to 32 units per rack means managing over 36,000 fibers.
- Rack-level success hinges on industry solutions for backplane design and fiber routing.
Full summary
Kishore Atreya, Sr. Director, Platform Product Management at Marvell, presents the company's co-packaged optics reference platform featuring a liquid-cooled 1 OU system with 16 6.4T light engines that integrate silicon photonics technology for electrical-to-optical signal conversion. He addresses the significant deployment challenge of managing over 36,000 fibers when scaling to 32 units per rack, emphasizing the need for industry solutions in backplane design and fiber routing for successful rack-level implementation.
Unlocking Memory Bandwidth
- Marvell's Structura CXL portfolio targets rising memory capacity and compute demands.
- Structura A packs 16 ARM cores for deep learning and inference workloads.
- Structura X enables memory expansion, mixing DDR4 and DDR5 with compression algorithms.
Full summary
Khurram Malik, Sr. Director, Product Marketing, CXL at Marvell, presents the company's Structura CXL product portfolio designed to address growing memory capacity and compute power demands. The portfolio includes Structura A with 16 ARM core processors for deep learning and inference workloads, and Structura X for memory expansion solutions that enable hyperscalers to combine DDR4 and DDR5 memory with compression algorithms.
Faster Cadence - Moving to 200G/Lane and Faster
- Acacia launched a silicon photonic Optical Engine family delivering 200G per lane for AI infrastructure.
- A new 1.6T PAM4 DSP marks Acacia's expansion into data center markets.
- Design emphasis on power efficiency and enhanced network performance.
Full summary
Tom Williams, VP, Marketing at Acacia , introduces their new silicon photonic Optical Engine product family designed to support AI infrastructure with 200Gig per lane capabilities across multiple applications. The company's development of a 1.6T PAM4 DSP demonstrates their expansion into data center markets while focusing on power efficiency and enhanced network performance.
Co-Packaged Optics Gains Momentum
- GlobalFoundries touts monolithic wafer technology and two-sided testing as CPO differentiators.
- Positioning itself as a key player in the co-packaged optics market.
- Focus is data center applications where scale-up networking dominates transmission needs.
Full summary
Kevin Soukup, SVP and GM of Silicon Photonics at GlobalFoundries, outlines the company's progress in co-packaged optics technology at OFC 2025, emphasizing their unique advantages in monolithic wafer technology and two-sided testing capabilities. Through strategic partnerships and advanced manufacturing processes, GlobalFoundries is positioning itself as a key player in the CPO market, particularly focusing on data center applications where scale-up networking dominates transmission needs.
Silicon Photonics Building Blocks: 1.6T Components
- Intel presents its OCI chiplet and 1.6 terabit-per-second components for pluggable transceivers.
- Over 8 million silicon photonics transceivers shipped to date.
- Expanding photonic manufacturing capacity at its New Mexico facility.
Full summary
Christian Urricariet, Senior Director of Product Marketing, Integrated Photonics Solutions at Intel, presents the company's latest advancements in silicon photonics at OFC 2025, including their OCI chiplet and 1.6 terabit per second components for pluggable transceivers. Building on their extensive experience in silicon photonics, Intel has achieved significant production milestones with over 8 million transceivers shipped and is expanding their photonic manufacturing capabilities at their New Mexico facility.
Next-Gen Switching: Co-Packaged Optics vs. Co-Packaged Copper
- Marvell showcases a co-packaged copper switch-tray design using substrate-mounted flyover wires at 224G.
- The liquid-cooled solution enables direct XPU ASIC to CPO engine connections.
- Supports large-scale multi-rack clusters up to 2,000 nodes with a single switching layer.
Full summary
George Hervey, Principal Architect at Marvell, showcases an innovative co-packaged copper design for switch trays that enhances passive copper performance through substrate-mounted flyover wires and 224G compatibility. The liquid-cooled solution enables direct XPU ASIC to CPO engine connections and supports large-scale multi-rack compute clusters up to 2,000 nodes with a single switching layer.
448G Connectivity: Key Requirements & Solutions
- Microsoft frames the shift from 224G to 448G around power budget and retimer challenges.
- Requirements include roughly 40 dB reach specifications alongside power and cost targets.
- Both copper and optical implementation approaches are on the table.
Full summary
Ashwin Gumaste, Principal AI Systems Architect at Microsoft, examines the industry's shift from 224G to 448G connectivity, focusing on power budget constraints and retimer solution challenges. He explores technical requirements including 40 dB reach specifications, power optimization targets, and cost considerations while discussing both copper and optical implementation approaches.
Gearbox-Free Electrical-Optical Co-Design for 448G Era
- Nubis argues for tight electrical-to-optical integration in the 448G era.
- Its approach eliminates power-consuming gearboxes.
- Optics can be driven directly from SerDes.
Full summary
Peter Winzer, Founder & CTO of Nubis Communications, emphasizes the importance of electrical-to-optical integration at the OIF 448G workshop, focusing on solutions that operate without power-consuming gearboxes and can be directly driven from SerDes.
448G Building the Future of High-Speed Connectivity Standards
- OIF's Interoperability Working Group is building a framework document for 448G standards.
- It covers 448G applications from long-reach down to chip-to-chip connections.
- Input is drawn from SerDes vendors, connector manufacturers, and end users across multiple standards bodies.
Full summary
Michael Klempa, Interoperability Working Group Chair at OIF, leads discussions at the 448G AI workshop to establish industry standards for high-speed connectivity. The initiative brings together multiple standards organizations and industry partners to develop a comprehensive framework document covering various 448G applications, from long-reach to chip-to-chip connections, while incorporating feedback from SerDes vendors, connector manufacturers, and end users.
Why 400G Systems Demand a New Era of Industry-Wide Collaboration
- The shift to 400G systems demands unprecedented collaboration across equipment vendors, component makers, and chip designers.
- OIF is coordinating industry-wide evaluation of circuit designs and modulation approaches.
- Power and reliability hurdles remain the main obstacles to 400G deployment.
Full summary
Cathy Liu, SerDes Architect at OIF, explains how the shift to 400G systems demands unprecedented collaboration between equipment vendors, component makers, and chip designers to overcome bandwidth constraints. She describes how OIF is coordinating industry-wide efforts to evaluate circuit designs and modulation approaches that will enable successful 400G deployment despite power and reliability hurdles.
Optical DSP Evolution - Pluggables and More
- 1.6T transceivers and power-efficient 3nm DSP devices emerge in 2025.
- Optical link reliability becomes essential for AI clusters.
- The optical ecosystem expands beyond traditional suppliers to meet growing demand.
Full summary
Chris Collins, VP of Sales & Marketing for Optical DSPs at Credo, outlines predictions for 2025 including the emergence of 1.6T transceivers and power-efficient 3nm DSP devices. He highlights how optical link reliability will be essential for AI clusters while the optical ecosystem expands beyond traditional suppliers to support growing market needs.
AI & Connectivity Drive 2025 Semiconductor Growth
- Robust semiconductor expansion is driven by AI advancements and cloud service provider growth.
- Automotive and industrial sector demand strengthens the outlook.
- EV features and infrastructure investments lead the way.
Full summary
Piyush Sevalia, Executive Vice President, Marketing at SiTime, forecasts robust semiconductor industry expansion in 2025, driven by AI advancements and cloud service provider growth. The semiconductor market's positive outlook is further strengthened by automotive and industrial sector demands, with developments in electronic vehicle features and infrastructure investments leading the way.
Vision AI in 2025
- Vision AI shifts toward edge computing and user-friendly deployment tools.
- Simplified tools make AI model development accessible to frontline workers.
- This enables broader workplace adoption of Vision AI solutions.
Full summary
Jim Lenox, Vice President of Systems Solutions at Sony Semiconductor, outlines predictions about Vision AI's shift toward edge computing and user-friendly deployment tools. He highlights how AI model development will become more accessible to frontline workers through simplified tools, enabling broader workplace adoption of Vision AI solutions.
Data Center Optimization Strategies
- Modern AI data centers are reaching 5 gigawatts and multi-million GPU clusters.
- Optimization spans every layer, from nanometer-scale silicon transistors to full racks.
- TEF convenes the entire AI infrastructure ecosystem to enable next-generation buildouts.
Full summary
Pete Del Vecchio, Data Center Switch Product Line Manager at Broadcom, presents at the Technology Exploration Forum for Internet Alliance 2025, highlighting how the event uniquely brings together the entire AI infrastructure ecosystem to address the massive scale of modern data centers, with some reaching 5 gigawatts and multi-million GPU clusters. He emphasizes the comprehensive optimization approach being applied across all components, from nanometer-scale silicon transistors to racks, as the industry collaborates to enable next-generation AI infrastructure capable of supporting systems the size of Manhattan.
Faster and Faster Networking Upgrade Cycles
- 112 gigabit SerDes (400G ports) giving way to 224 gigabit SerDes enabling 800G for GPU platforms.
- Accelerator platforms now advance every 18 months or less.
- Ecosystem moving toward 440 gigabit SerDes networks for next-generation AI.
Full summary
Baron Fung, Senior Research Director at Dell'Oro Group, examines data center infrastructure markets with emphasis on servers and connectivity, tracking the evolution from current 112 gigabit SerDes supporting 400 gigabit ports to emerging 224 gigabit SerDes enabling 800 gigabit speeds for GPU platforms. He highlights that accelerator platforms now advance every 18 months or less, driving the ecosystem toward Ethernet-based solutions and the upcoming transition to 440 gigabit SerDes networks to support next-generation AI and accelerated computing requirements.
Overcoming 400G Technology Challenges
- 400G advancement requires collaboration across connector, cable, silicon, optical, and system vendors.
- Challenging 400G conditions demand precise link training protocols and standardized error correction.
- Robust Ethernet standards are needed to ensure 400G interoperability.
Full summary
Jim Hsieh, Senior Technical Manager at Mediatek, presents on the critical need for industry-wide collaboration to advance 400G technology, emphasizing cooperation among connector manufacturers, cable vendors, silicon vendors, optical vendors, and system providers. He explains that 400G's challenging initial conditions require precise link training protocols, standardized error correction methodologies, and robust Ethernet standards to ensure interoperability and reliable connections across all industry participants.
Ethernet Scaling Challenges & Solutions
- Ethernet remains the preferred choice for scale-up and scale-out AI applications.
- Unprecedented demand spans network connectivity, semiconductors, and testing.
- TEF is a critical venue for identifying technologies that must integrate to solve interoperability challenges.
Full summary
Hani Daou, Business Development Manager at Multilane, presents on behalf of the Ethernet Alliance at the Technology Exploration Forum, discussing how Ethernet remains the preferred choice for scale-up and scale-out AI applications amid unprecedented demand for network connectivity, semiconductors, and testing. He emphasizes the forum's role as a critical venue for identifying technologies that must integrate seamlessly to address interoperability challenges and meet the demanding requirements of cloud service providers and end users with their growing appetite for AI-based applications.
CEI-448G Framework: New Standards AI Interconnect Networks
- OIF publishes the CEI-448G framework for next-generation AI interconnect networks.
- It identifies future CEI-448G XSR, VSR, and LR variants as follow-on projects.
- Calls for collaboration across IEEE 802.3 Ethernet, OCP, SNIA, and UEC.
Full summary
Cathy Liu, SerDes Architect at OIF, presents the newly published CEI-448G framework, a collaborative achievement by OIF members across AI hyperscalers, system vendors, and component manufacturers that establishes common guidelines for next-generation AI interconnect networks. The framework serves as foundational work identifying future projects including CEI-448G XSR, VSR, and LR variants, while emphasizing the need for collaboration among standards bodies such as IEEE 802.3 Ethernet, OCP, SNIA, and UEC.
Network-as-a-Service: Scaling for AI and Cloud Connectivity Demands
- InsidePacket's NaaS platform runs on merchant silicon and white box hardware.
- It targets growing demand for high-capacity connections, particularly in AI applications.
Full summary
Eli Karpilovski, CEO of InsidePacket, presents their network-as-a-service (NaaS) platform designed to run on merchant silicon and white box hardware, meeting the growing demand for high-capacity connections, particularly in AI applications.
Introducing "Coherent-Lite" for Data Center Connectivity
- Marvell's Achyut Shah introduces coherent-lite for intermediate-reach data center connectivity.
- It combines coherent modulation, O-band optics, and a re-architected DSP for links from 2 km to 20 km.
Full summary
Achyut Shah, SVP and GM of Connectivity, introduces the company's new "coherent-lite" technology, addressing intermediate-reach connectivity needs in data centers. This solution combines coherent modulation with O-band optics and a re-architected DSP to provide lower latency, cost, and power consumption for links ranging from 2 km to 20 km.
Custom Silicon & Accelerated Infrastructure for AI
- Marvell's Chris Koopmans cites strong hyperscaler market growth and Marvell's custom compute and networking position.
- The focus is tailored solutions for large customers to expand market opportunities for AI infrastructure.
Full summary
Chris Koopmans, Chief Operations Officer, discusses the significant growth of the hyperscaler market and Marvell's strong position in delivering custom compute and networking solutions for AI and accelerated infrastructure. He emphasizes Marvell's focus on creating tailored solutions for large customers, aiming to expand market opportunities and develop new capabilities that provide value across diverse applications.
Custom Silicon is the Driver of Optimized AI Infrastructure
- Marvell's Raghib Hussain sees optimized AI infrastructure built on custom silicon for data centers.
- Partnerships with Amazon and Meta show customization delivering power and cost savings at scale.
Full summary
Raghib Hussain, President of Products and Technologies, highlights the growing trend of developing optimized AI infrastructure using custom silicon for data centers. Hussain discusses Marvell's partnerships with major tech giants like Amazon and Meta, emphasizing the value of customization in achieving power and cost savings at scale.
Marvell's Breakthrough High Bandwidth Memory Architecture
- Marvell's Will Chu announces partnerships with major HBM providers for custom high bandwidth memory.
- Custom HBM cuts power consumption, boosts memory capacity, and improves TCO for AI data centers.
Full summary
Will Chu, SVP and GM of Custom Compute and Storage BU, announces a partnership with major HBM (high bandwidth memory) providers to deliver custom HBM solutions for next-generation AI data centers. This enables significant reductions in power consumption, increased functionality, and improved memory capacity, resulting in better performance and enhanced TCO for Marvell's customers.
Impactful AI Connectivity
- Astera Labs' Ahmad Danesh names three data center challenges: AI workloads, real-time reasoning, and rapid deployment of new accelerators.
- Its Ethernet retimers, Smart Fabric switch, and PCIe 6 retimers pair with the Cosmos software stack to improve connectivity and observability.
Full summary
Ahmad Danesh, Sr. Director of Product Management at Astera Labs, outlines three key challenges in data center infrastructure: AI workloads, real-time reasoning, and rapid deployment of new accelerators. Astera Labs addresses these issues through their Ethernet retimers, Smart Fabric switch, and PCIe 6 retimers, combined with their Cosmos software stack to enhance connectivity and observability.
Custom Silicon for Hyperscale Data Centers
- Marvell's Nigel Alvares details custom silicon co-developed with hyperscalers for optimized performance, power, and cost.
- He announces Meta's FB NIC, open-sourced to OCP and built on Marvell's 5-nanometer platform.
Full summary
Nigel Alvares, VP of Global Marketing at Marvell, discusses the company's collaboration with hyperscalers to create custom silicon for optimized performance, power, and cost. He announces Meta's release of the FB NIC, a network interface controller, which Marvell has open-sourced to the OCP community, demonstrating the use of Marvell's 5-nanometer platform for tailored silicon solutions.
3nm Drives PCIe Gen 7
- Marvell's Annie Liao discusses PCIe retimers addressing the challenge of rising interconnect speeds.
- Its Gen 6 and Gen 7 solutions extend trace lengths to support upcoming PCI advancements.
Full summary
Annie Liao, Product Management Director at Marvell, discusses PCI's evolution as a standard protocol for computer system connectivity and the challenges of increasing speeds. Marvell is addressing these challenges with PCI retimers, showcasing Gen 6 and Gen 7 solutions that extend trace lengths and support upcoming advancements in PCI technology.
800G Linear Receive Optics Connected to 51.2T Switch
- Credo demoed its Dove 850 Linear Receive Optics (LRO), where only the transmit path uses a DSP.
- Placing a DSP solely on the transmit path for retiming and equalization unlocks dramatic power savings.
Full summary
Easwar Sankar, Optical FAE Director at Credo, demos the company's new Linear Receive Optics (LRO) product, Dove 850. In an LRO transceiver, or Active Optical Cable (AOC), only the transmit path from the electrical input to the optical line side output includes a DSP for signal retiming and equalization. This unlocks dramatic power savings.
Intel's Optical I/O Chiplet Co-Packaged with Server CPU
- Intel unveiled its first Optical Compute Interconnect (OCI) chiplet, a high-density optical IO solution.
- The OCI chiplet supports up to 4 terabits per second bi-directionally to interconnect CPUs and high-performance chips.
Full summary
Christian Urricariet from Intel's Silicon Photonics Product Division, unveiled the company's first Optical Compute Interconnect (OCI) chiplet, a high-density optical IO solution capable of supporting up to 4 terabits per second bi-directionally, enabling it to interconnect CPU or other high-performance chips.
Intel's Silicon Photonics Roadmap
- Intel is shifting from full transceiver modules to supplying key chipsets for the pluggable silicon photonics market.
- Intel announced 1.6 Tbps components supporting 200G/lane for both DR and FR formats at OFC24.
Full summary
Intel is making a strategic shift from providing full transceiver modules to supplying key chipsets for the growing pluggable market in silicon photonics. At OFC24, Intel also announced 1.6 Tbps components supporting 200G/lane for both the DR and FR formats. Amit Nagra, VP and GM of the Silicon Photonics Product Division, shares highlights.
Transmit-Retimed Optical DSPs Yield Huge Power Savings
- Marvell's Spica Gen2-T is a transmit-only DSP enabling a new Transmit Retimed Optical (TRO) module.
- The TRO module cuts power consumption by 40% while preserving flexibility and scalability for AI clusters.
Full summary
Marvell VP of Product Marketing, Xi Wang, highlighted the rising demand for optical connectivity in AI cluster. Marvell has introduced a new product, Spica Gen2-T, a transmit-only DSP that enables a new type of optical module, the Transmit Retimed Optical (TRO) module, which can reduce power consumption by 40% while ensuring flexibility and scalability.
New 800ZR and 800ZR+ Pluggables Extend Reach
- Marvell's Orion DSP uses probabilistic constellation shaping (PCS) for hyperscalers needing greater distance.
- PCS extends 800G reach beyond 1,000 km, versus 500 km for 800G ZR+.
Full summary
Stephen Adolph, AVP of CDSP Product Line Management at Marvell, introduces Orion DSP that uses probabilistic constellation shaping (PCS), crucial for hyperscale network operators needing increased network distance. PCS extends 800G reach to over 1,000 km, an improvement over 800G ZR+ at 500 km.
A New Class of Silicon Photonics for AI Data Centers
- Marvell unveiled a 3D SiPho engine delivering 6.4 Tbps with 200G I/O for AI applications.
- The 3D SiPho Engine offers 2x bandwidth density and 30% lower power per bit versus 100 Gbps interfaces.
Full summary
Loi Nguyen, EVP and GM of Optical at Marvell, unveiled their 3D SiPho engine, a silicon photonics engine that delivers 6.4 Tbps, enhancing speeds for AI applications. Featuring 200G I/O, the 3D SiPho Engine delivers 2x the bandwidth and input/output (I/O) bandwidth density, and 30% lower power per bit versus devices with 100 Gbps electrical and optical interfaces.
Massive Upgrades Coming with 200G per Lane Channels
- Marvell unveiled Nova 2, an optical DSP addressing the shift to 200G per lane.
- Nova 2 enables 1.6 Tbps optical transceiver modules for next-generation AI connectivity and compute.
Full summary
Marvell's Vice President of Product Marketing, Xi Wang, unveiled a new product, Nova 2 designed to address the shift to 200G. Nova 2, an optical DSP, facilitates the construction of 1.6 Tbps optical transceiver modules, enhancing connectivity and computing power for next-generation AI.
800G, LPO, and Other Big Trends at #OFC24
- OpenLight highlighted the transition to 800G and the coming need for 1.6 Tbps.
- OpenLight partnered with Jabil to mainstream silicon photonics, moving toward 400G and 200G lanes.
Full summary
Adam Carter, CEO of OpenLight, highlighted the transition to 800G and the future need for 1.6 Tbps. Carter also discussed OpenLight's strategic partnership with Jabil to mainstream silicon photonics, the transition to 400G, and the future direction towards 200G lanes.
Scaling Silicon Photonics to Meet the AI Challenge
- OpenLight CEO Adam Carter questioned whether the industry underestimates optical-module manufacturing needs for AI.
Full summary
Are we underestimating the manufacturing requirements for optical modules needed to AI? Adam Carter, CEO from OpenLight, shares some insights.
Advanced DFB Laser Arrays for I/O in AI Clusters
- Sivers Photonics supplies DFB laser arrays for Ayar Labs' SuperNova optical interconnect.
- SuperNova targets AI/ML clusters, disaggregated data centers, 6G networks, and phased array sensor systems.
Full summary
Sivers Photonics is supplying its DFB laser arrays for Ayar Labs’ SuperNova optical interconnect for AI/ML clusters, disaggregated data centers, 6G networks, phased array sensor systems and etc. Anders Storm, CEO from Sivers Semiconductors explains.
AI Chiplets and Optical Communications
- Alphawave Semi's Tony Chan Carusone predicts AI capabilities enhanced through customized hardware with chiplets.
- He forecasts a surge in hardware demand and a growing number of semiconductor companies.
Full summary
Tony Chan Carusone, Chief Technology Officer for Alphawave Semi, predicts AI capabilities will be enhanced through the deployment of customized hardware with chiplets, a surge in demand for hardware, and an increase in semiconductor companies.
Silicon Photonics & Novel Materials
- GlobalFoundries' Vikas Gupta forecasts silicon photonics ecosystem growth, especially in packaging led by nontraditional OSATs.
- He predicts more use of novel materials like lithium niobate, barium titanate, and organic polymers.
Full summary
Vikas Gupta, Senior Director of Product Management at GlobalFoundries, forecasts growth in the Silicon photonics ecosystem, especially in packaging, with nontraditional OSATs leading and the rise of a cottage industry around this technology. Gupta also predicts an increase in the use and development of novel materials such as lithium niobate, barium titanate, and other organic polymers.
AI Clusters and Custom Silicon in 2024
- Marvell's Noam Mizrahi forecasts larger AI clusters needing higher bandwidth and ultra-complex custom silicon ASICs.
- He predicts a shift from AI training to inference, requiring more optimized infrastructure with unique network features.
Full summary
Noam Mizrahi, EVP and Corporate CTO at Marvell, forecasts the growth of larger and more demanding AI clusters will require higher bandwidth connectivity and the development of ultra-complex custom silicon ASICs, optimized for specific use cases. Mizrahi also predicts a shift from training AI models to inference, necessitating a more optimized infrastructure with unique network features.
AI Reshaping the Ethernet Landscape
- 650 Group's Alan Weckel says AI is spawning three new networks with faster speeds and a vendor product race.
- High-speed Ethernet port adoption is growing rapidly, with Nvidia entering Ethernet semiconductors and systems.
Full summary
Alan Weckel, Founder and Technology Analyst at 650 Group, examines AI's influence on the Ethernet market, highlighting the creation of three networks with faster speeds and a vendor race for new products. He discusses the rapid growth in high-speed Ethernet port adoption and the expanding data center switching market, noting Nvidia's entry into Ethernet semiconductors and systems as a key development.
Unlocking AI's Potential: Connectivity and Collaboration
- Alphawave Semi stresses connectivity and industry collaboration as key to advancing AI technologies.
- Alphawave contributes chiplets, custom silicon, and die-to-die IP and transceivers for AI processor connectivity.
Full summary
Tony Chan Carusone, Chief Technology Officer of Alphawave Semi, emphasizes the importance of connectivity and industry collaboration in advancing AI technologies across multiple fronts. He highlights Alphawave Semi's contributions in chiplets and high-speed series technologies, including custom silicon solutions and IP offerings for die-to-die interfaces and transceivers for AI processor connectivity.
Optimizing Networking for AI Scale and Performance
- Astera Labs highlights the diverse requirements of different AI network types as networks expand.
- Astera's PCIe and Ethernet retimers provide intelligent connectivity to address channel challenges in AI architectures.
Full summary
Christopher Blackburn, System Architect & Director of Field Applications Engineering at Astera Labs, explores the challenges and future of AI networks, focusing on the diverse requirements of different network types and the need for optimization as networks expand. He discusses how Astera Labs' product line, including PCIe and Ethernet retimers, offers intelligent connectivity solutions to address channel challenges in various AI architectures.
Scaling Protocols and Connections for AI
- TE Connectivity's Ashika Pandankeril Shaji sees growing need for high-bandwidth, low-latency multi-protocol products.
- She emphasizes density and scalability from backplanes to internal cabling for technologies like CXL.
Full summary
Ashika Pandankeril Shaji, Staff System Architect at TE Connectivity, explores the growing need for high-bandwidth, low-latency products that support various protocols in AI applications. She emphasizes the importance of density and scalability in connectivity solutions, from backplanes to internal cabling, to meet the demands of emerging technologies like CXL.
Unleashing CXL Tech's Potential in AI & Data Center Evolution
- 650 Group's Alan Weckel positions CXL to compete with NVLink for enhancing AI and machine learning servers.
- Growing bandwidth demand requires new and multiple switches per rack, with spending shifting from cloud to AI.
Full summary
Alan Weckel, Founder and Technology Analyst at 650 Group, discussed the potential of CXL technology to compete with NVLink, emphasizing its importance in enhancing servers for AI and machine learning. Weckel also noted the rapidly growing demand for bandwidth, necessitating new high switches and multiple switches per rack, and highlighted the shift in spending from cloud to AI, likening it to the significant architectural shift brought about by cloud technology 20 years ago.
Democratizing Networking with SONiC
- Broadcom democratizes networking with open-source SONiC, bringing hyperscaler features to all users.
- Enhanced enterprise-class SONiC and silicon telemetry help customers quickly root-cause network and application issues.
Full summary
Kamran Naqvi, Principal Network Architect at Broadcom, discussed the company's efforts to democratize networking by making features previously exclusive to hyperscalers available to all users, including the Sonic software, an open-source network operating system. Broadcom has enhanced Sonic to be more enterprise-class, leading to increased adoption among enterprise customers, and has enabled silicon telemetry features in its silicon, which can help customers quickly identify the root cause of network or application performance issues.
CPO Switches are Here!
- Broadcom's Near Margalit says the company has tackled the main technical challenges of deploying CPO switches.
- Focus now shifts to proving reliability and cost-effectiveness of silicon photonics and shortening time to market.
Full summary
Broadcom's GM and VP of Optical Systems Division, Near Margalit, announced that the company has successfully tackled the main technical challenges of deploying CPO switches and is now focusing on demonstrating the reliability and cost-effectiveness of the core silicon photonics technology. Margalit also addressed concerns about the reliability of the laser component and the time to market, stating that Broadcom is working to shorten the time between the availability of CPO technology for integration with the switch and its market launch.
Scaling AI Clusters: Optical Connectivity's Key Role in Data Transport
- Marvell's Radha Nagarajan stresses optical connectivity for managing data transport as AI clusters grow.
- Marvell's 1.6 DSP for the 1.60 generation is ready to meet demand in AI-centric data centers.
Full summary
Radha Nagarajan, SVP and CTO of Optical and Cloud at Marvell, emphasized the importance of optical connectivity in managing data transport as AI clusters increase in size. With the introduction of a 1.6 DSP for the 1.60 generation, Marvell is ready to meet the growing demand for optical connectivity solutions in AI-centric data centers.
Faster Interconnects for AI Data Centers
- Multilane's Hani Daou cites rising compute needs driving investment in 100 terabit AS6 and 200 gigabit per Lambda optics.
- Multilane sees high demand for its 800 gig systems and copper interconnect test solutions serving chip vendors and cloud providers.
Full summary
Hani Daou, Business Development Manager at Multilane, emphasized the need for data center upgrades due to increasing compute power requirements, with investments being directed towards technologies like 100 terabit AS6 and 200 gigabit per Lambda Optics. Multilane, currently experiencing high demand for its 800 gig systems and copper interconnect test solutions, is well-positioned to support semiconductor vendors, cloud service providers, and interconnect vendors with a strategic roadmap for R&D investment and bandwidth scaling.
Harnessing CXL for AI/ML Interconnectivity
- OCP's Siamak Tavallaei stresses CXL for interconnecting large machine learning systems with a fundamental interconnect standard.
- CXL can link 10,000 units, petabytes of storage, and hundreds of terabytes of shared memory for device and host communication.
Full summary
Siamak Tavallaei, CXL Advisor to the Board at Open Compute Project, emphasizes the importance of CXL in enabling interconnection of large systems for machine learning and artificial intelligence, and the need for a fundamental standard for interconnectivity. He asserts that CXL can facilitate the interconnection of 10,000 units, petabytes of storage, and hundreds of terabytes of memory in a shared environment, promoting device-to-device and host-to-host communication.
Future of Data Centers: Chiplets, Bandwidth & AI-Intensive Workloads
- OCP ODSA lead Bapi Vinnakota highlights chiplets' efficiency in building heterogeneous systems for growing bandwidth needs.
- Chiplet-based systems will be crucial for AI-intensive data centers, with open interfaces as the optimal integration path.
Full summary
Bapi Vinnakota, the ODSA Project Lead at Open Compute Project, emphasized the growing need for more bandwidth and diverse types of compute in data centers, highlighting the efficiency of chiplets in building heterogenous systems. He concluded that chiplet-based systems will be crucial in future data centers, especially those with AI-intensive workloads, and advocated for open interfaces as the optimal way to integrate systems and chiplet devices from various vendors.
Advancing the Open Chiplet Economy
- OCP's Cliff Grossner describes standardizations letting companies build a chiplet and publish an electronic data sheet for others' design tools.
- OCP revealed plans to establish a marketplace for chiplets.
Full summary
Cliff Grossner, VP Market Intelligence and Innovation at Open Compute Project (OCP), discusses the advancements in the open chiplet economy vision, including standardizations that allow companies to build a chiplet and create an electronic data sheet for others to use in their design tools. Grossner also revealed plans to establish a marketplace for chiplets.
What's Next for Chiplets
- Synopsys highlights cost-effective chiplets over monolithic chips as the industry nears the limits of electronics.
- That physical ceiling makes a shift to chiplets increasingly likely.
Full summary
Yervant Zorian, Fellow & Chief Architect at Synopsys, highlights the potential of cost-effective chiplets over monolithic chips, suggesting the industry is nearing the limits of electronics, thus making a shift to chiplets more likely.
Integrating Chiplets into Complete Systems
- Thrace Systems, leading the CDX work stream under ODSA, announced an upcoming white paper on chiplet integration workflows.
- The paper covers all aspects of chiplet integration and will publish on the Open Compute Project website.
Full summary
David Ratchkov, founder of Thrace Systems and lead of the CDX work stream group under ODSA in the Open Compute Project, has announced the upcoming release of a detailed white paper on chiplet integration workflows. The paper will cover all aspects of chiplet integration and will be available on the Open Compute Project's website once released.
Maximizing Customer Engagement with Nokia's Latest Innovations
- Nokia's Roland Thienpont showcases 800G, FP5 silicon, DeepField DDoS, and automation technologies at MPLS WC.
- He reports strong customer engagement and detailed in-depth discussions at the event.
Full summary
Roland Thienpont, Director IP Division Product Marketing from Nokia explains: - Why he's excited to be at MPLS WC with detailed in-depth customer discussion - How they are showcasing 800G, FP5 silicon, DeepField DDoS, and automation technologies - How he's seeing strong customer engagement and expectation to return next year
Transforming Data Centers with PCIe, CXL and Ethernet
- Astera Labs enables PCI Express infrastructure to scale with growing GPUs and AI accelerators.
- It partnered with Lenovo and AMD on CXL memory expanders and showcased an ethernet retimer for high-speed rack connectivity.
Full summary
At the OCP 2023 event,Thad Omura, SVP of Business and Corporate Development at Astera Labs, discussed the company's advancements in scaling AI platforms and cloud infrastructure, including enabling PCI Express infrastructure to scale with increasing GPUs and AI accelerators. Astera Labs has also partnered with Lenovo and AMD to offer unprecedented memory capacity using their CXL memory expanders, and showcased their industry-leading ethernet retim used for active electrical cases, allowing high-speed connectivity in the rack and from switch to switch.
Broadcom's new 25.6T Router Super Chip
- Broadcom unveils the Qumran3D, the industry's first 5-nanometer 25.6 terabit router chip, with up to 66% power savings and 80% space reduction.
- It supports up to 800GE ports using 100Gb/s PAM-4 SerDes and massive on-chip forwarding databases, eliminating companion devices.
Full summary
Henry Wu, Technical Director at Broadcom, unveils the Qumran3D, the industry's first 5-nanometer 25.6 terabit router chip, offering up to 66% power savings and 80% router space reduction. The device, designed to combat cybersecurity threats, supports high-speed, high-density port interfaces up to 800GE leveraging best-in-class 100Gb/s PAM-4 SerDes. The design also enables massive on chip forwarding databases, eliminating the need for companion devices
CXL for AI-Powered Data Centers
- CXL Consortium's Siamak Tavallaei addresses AI and ML challenges for system architects at the OCP Global Summit.
- He proposes CXL with UCIe transport for die-to-die and photonics to build large ML systems with larger memory blocks.
Full summary
Siamak Tavallaei, CXL Advisor to the Board at CXL Consortium, addressed the challenges artificial intelligence and machine learning pose to system architects at the OCP Global Summit. He proposed the use of the CXL specification, UCIe as a transport for running CXL for die to die, and interconnect techniques like photonics to construct large machine learning systems, enabling larger memory blocks and interfaces with emerging memory technologies.
800ZR/ZR+ OSFP for Regional Data Center Interconnects
- Marvell's 800 Gbps ZR/ZR+ coherent pluggable module converts a switch or router into a transport platform.
- Leveraging Marvell's DSP, TIAs, drivers, and silicon photonics, it enables 25.6 terabits single-fiber capacity between data centers.
Full summary
Radha Nagarajan, SVP and CTO of Optical and Cloud at Marvell, highlighted the company's new 800 Gbps ZR/ZR+ coherent pluggable module designed to enhance data center connectivity by converting a switch or router into a transport platform. The module, which leverages Marvell's capabilities at 800 gig, including the DSP, high-speed TIAs, drivers, and silicon photonics, enables a single fiber capacity of 25.6 terabits between data centers, facilitating larger data aggregation.
Accelerating the Chiplet Economy
- OCP ODSA lead Bapi Vinnakota describes CDXML, a new language developed with JEDEC to describe chiplets globally.
- The open chiplet economy is moving from theory to products, with an experience center showcasing work from 11 companies.
Full summary
Bapi Vinnakota, ODSA Project Lead at Open Compute Project, highlighted the advancements in the open chiplet economy, including the development of a new language, CDXML with JEDEC, to describe chiplets globally and aid in tool flows and design searches. The project has also seen progress in interfaces, with the open chiplet economy transitioning from theory to tangible products and prototypes, as demonstrated by an experience center showcasing chiplet-based products, IP, and workflow from 11 companies.
Accelerating Virtual 5G Distributed Unit Processing
- Marvell's Joel Brand details silicon optimized for the RU, DU, and now the virtualized DU.
- The virtualized DU offloads functions to host servers aided by dedicated-silicon accelerator cards.
Full summary
In the drive toward O-RAN and v-RAN, silicon vendors are racing toward smaller geometries, and Marvell is on the leading edge with portfolio optimized for the RU, DU and now the virtualized DU, says Joel Brand, Senior Director, Product Marketing, Marvell. The idea with the virtualized DU is to process some of the functionality in a host server leveraging cloud technologies and a new generation of accelerator cards powered by dedicated silicon. Download AvidThink's MWC 2022 Report Collection to explore exclusive insights and research findings on hot topics covered at MWC 2022.
MWC Americas: Silicon powers the network
- Marvell's Joel Brand shares a perspective on the silicon that powers the mobile networks we all rely upon.
Full summary
Introducing CXL Memory Pooling
- Astera Labs demonstrates the industry's first CXL memory pooling to cut memory stranding and cloud server TCO.
- Its Leo controller runs memory pooling today with CXL 1.1-capable 4th Gen Intel Xeon processors.
Full summary
Astera Labs has demonstrated the industry’s first CXL memory pooling solution to reduce memory stranding, optimize memory utilization and reduce cloud server TCO. Ahmad Danesh, Sr. Director, Product Management, Astera Labs demonstrates how memory pooling can be deployed today with Leo and CXL 1.1-capable 4th Gen Intel Xeon processors.
Rethinking Data Center Fabrics
- Enfabrica's founders argue data center fabric architecture must be rethought to overcome I/O scaling limits.
- Their approach maps to OCP Summit themes of openness, efficiency, scalability, and sustainability.
Full summary
Roshan Sankar and Shrijeet Mukherjee, founders of Enfabrica, a Silicon Valley stealth start-up, discuss how we need to rethink fabric architecture to overcome challenges in I/O scaling and address the key themes at #OCPSummit2022 of openness, efficiency, scalability, and sustainability.
OCP progress with ODSA Chiplets and Bunch-of-Wires Interface
- OCP's Bapi Vinnakota updates progress on the ODSA chiplet initiative and its Bunch-of-Wires interface.
Full summary
Bapi Vinnakota, project lead for the Open Compute Project’s Open Domain-Specific Architecture (ODSA) initiative, provides an update on chiplet architecture.
Energy-Efficient Data Centers, Healthcare, Mobility
- DuPont's Jake Joo expects energy-efficient data centers, healthcare, and mobility to drive 2022.
Full summary
Jake Joo, Technical Manager, DuPont Silicon Valley Technology Center, shares predictions for 2022. Download AvidThink's 2021 Select Report Collection to explore strategies and opportunities in the Telco, Private Mobile Networks, Service Assurance, SD-WAN and Open RAN space.
Automotive Ethernet, Car-to-Cloud, Custom Silicon
- Marvell's Will Chu points to automotive Ethernet, car-to-cloud, and custom silicon in 2022.
Full summary
Will Chu, SVP & General Manager, Automotive at Marvell, shares predictions for 2022. Download AvidThink's 2021 Select Report Collection to explore strategies and opportunities in the Telco, Private Mobile Networks, Service Assurance, SD-WAN and Open RAN space.
Coherent Pluggables, Cloud RAN, Cloud Silicon
- Marvell's Radha Nagarajan flags coherent pluggables, cloud RAN, and cloud silicon for 2022.
Full summary
Radha Nagarajan, SVP & CTO, Optical & Copper Connectivity at Marvell, shares predictions for 2022. Download AvidThink's 2021 Select Report Collection to explore strategies and opportunities in the Telco, Private Mobile Networks, Service Assurance, SD-WAN and Open RAN space.
Edge Computing, Composable, Silicon, and Data Center Sustainability
- Open Compute Project's Cliff Grossner highlights edge computing, composability, silicon, and data center sustainability for 2022.
Full summary
Cliff Grossner, Vice President, Market Intelligence at Open Compute Project, shares predictions for 2022. Download AvidThink's 2021 Select Report Collection to explore strategies and opportunities in the Telco, Private Mobile Networks, Service Assurance, SD-WAN and Open RAN space.
New Silicon and Open Software Driving a New Ecosystem
- EdgeQ's Vinay Ravuri describes strong 5G interest from operators, enterprises, and cloud service providers.
- New silicon and open software are transforming box makers and creating new markets.
Full summary
There’s a plethora of interest in the 5G space from operators to enterprises and cloud service providers. In this video, Vinay Ravuri, CEO and Founder of EdgeQ, talks about how box makers are transforming with the emerging 5G market and how open software is driving a new set of markets.
What's Next for NFVI
- Ericsson's Lars Mårtensson points to containers and Kubernetes as the next steps for NFV infrastructure.
- He also highlights the move toward the edge in NFV's progression.
Full summary
Lars Mårtensson, VP & Head of Solution Area Cloud and NFVi & Head of Ericsson Silicon Valley, shares his thoughts on the progress of NFV and what's next including containers and Kubernetes as well as the move toward the edge.