Technology Exploration Forum Showcase

Alan Weckel, Founder and Technology Analyst at 650 Group, presents from TEF 2025 on the $200 billion Ethernet switching market opportunity driven by AI infrastructure requiring multiple interconnected networks for GPUs and XPUs, with bandwidth growth accelerating from 30-40% to 70-80% CAGR. He projects data centers will exceed one billion ports within years, creating multi-billion dollar opportunities across LPO, LRO, ACC, AEC, and CPO transceiver technologies as the industry experiences 4x revenue increases alongside dramatic expansion in speeds and capacity.

Arihant Jain, Manager, Systems Engineering at Arista Networks, examines scale-out networking architectures and interconnect technologies while highlighting how power, cooling, and space constraints are increasingly driving data center network design decisions alongside traditional requirements. He emphasizes Ethernet's expanding role across scale-up and scale-out applications, anticipates 1.6 terabit deployments with hybrid cooling solutions by 2026, and identifies scale-across connectivity between geographically distributed data centers as a key deployment trend for the coming year.

Pete Del Vecchio, Data Center Switch Product Line Manager at Broadcom, presents at the Technology Exploration Forum for Internet Alliance 2025, highlighting how the event uniquely brings together the entire AI infrastructure ecosystem to address the massive scale of modern data centers, with some reaching 5 gigawatts and multi-million GPU clusters. He emphasizes the comprehensive optimization approach being applied across all components, from nanometer-scale silicon transistors to racks, as the industry collaborates to enable next-generation AI infrastructure capable of supporting systems the size of Manhattan.

David B. Kiddoo, Executive Director / CEO of CCCA and IWCS, explains his organizations' sponsorship of the Ethernet Alliance conference that brings together decision makers from Meta, Microsoft, and Hewlett Packard to address Ethernet for AI and the convergence of power and data supporting AI and quantum computing infrastructure. The conference enables the interconnect and network infrastructure industry to learn directly from technology providers about required innovations, necessary codes and standards, and how to allocate limited resources effectively to advance AI and quantum computing technologies.

Ravi Shah, Director, Corporate Strategy at Cisco Systems, discusses how AI use cases are driving unprecedented infrastructure adoption as hyperscalers deploy XPUs and GPUs requiring proportional networking growth across scale-up, scale-out, and scale-across architectures. He explains the industry's focus on achieving 400 gigabit speeds through ecosystem collaboration addressing engineering challenges, while emphasizing the forum's role in enabling thought leaders to leverage open standards like Ethernet and advance AI infrastructure development.

Adee Ran, Architect of Ethernet at Cisco Systems, discusses his standards work with IT and UltraEthernet, emphasizing the collaborative effort required across industries to develop next-generation networking technologies. He explains that achieving mature next-generation technology requires inventing numerous components, such as optical modules with doubled improvements in signal integrity, power consumption, cost, and manufacturing yield, though the timeline for these innovations remains uncertain.

Baron Fung, Senior Research Director at Dell'Oro Group, examines data center infrastructure markets with emphasis on servers and connectivity, tracking the evolution from current 112 gigabit SerDes supporting 400 gigabit ports to emerging 224 gigabit SerDes enabling 800 gigabit speeds for GPU platforms. He highlights that accelerator platforms now advance every 18 months or less, driving the ecosystem toward Ethernet-based solutions and the upcoming transition to 440 gigabit SerDes networks to support next-generation AI and accelerated computing requirements.

Peter Jones, Chair of the Ethernet Alliance and Cisco Systems employee, addresses the accelerating pace of Ethernet speed transitions at the second TF Ethernet for AI event, noting that 400 gigabit Ethernet is emerging before 200 gigabit is fully deployed. He emphasizes that the industry must focus on "just enough" rather than attempting everything at once, while highlighting Ethernet's consistent success over competing technologies.

John D'Ambrosia, Chair, IEEE P802.3dj Task Force at the Ethernet Alliance, discusses the evolution of 400 Gbit per second signaling for Ethernet in AI applications, noting that the next upgrade requires collaboration from all stakeholders across the industry ecosystem. He explains that the Ethernet Alliance facilitates this industry-wide collaboration through TEF events and partnerships, recognizing that faster consensus-building among manufacturers, material providers, and component makers accelerates progress toward solutions.

David Rodgers, Sr. Business development manager- EXFO and President & Events chair - Ethernet Alliance, examines the bifurcated state of network interoperability, contrasting hyperscalers like AWS optimizing AI-focused ecosystems with Ethernet standards prioritizing cross-vendor interoperability for broader markets. He highlights the Ethernet Alliance's evolving roadmap, first released in 2015 and now updated quarterly online, which tracks industry technologies, speeds, and interface nomenclatures to guide the industry through rapid changes in Ethernet technology.

John D'Ambrosia, Chair, IEEE P802.3dj Task Force at IEEE, discusses the working group's progress on 400 Gbit per second Ethernet signaling, covering modulation schemes, forward error correction, channel characteristics, and various fiber options including hollow core and multi-core fiber. He announces an IEEE workshop in late February to examine fiber technologies, emphasizing the goal of effective information transmission across different channel types as high-speed Ethernet development continues to advance.

John Calvin, Senior Strategic Planner at Keysight Technologies, presents from the 2025 Ethernet Alliance hosted TEF event in Mountain View, discussing 448 gig technology and deployment barriers driven by hyperscaler growth and data center demands. He addresses challenges including higher order modulation formats, next generation connectors, and channel considerations, noting that engineering choices for the next speed grade remain under discussion at the event.

Hadrien Louchet, Product Planner at Keysight Technologies, presents at a technology exploration forum on AI networking's future, noting that while 1.6T Ethernet deployment has begun and hyperscalers are planning for 3.2T Ethernet, the industry must navigate critical trade-offs between performance, power efficiency, reliability, and supply chain security as 400G signaling advances from lab to product. Louchet explains that Keysight, as a test and measurement expert, works with customers to understand testing requirements at these speeds and prepares products to support large-scale deployment of next-generation AI networking infrastructure.

Jim Hsieh, Senior Technical Manager at Mediatek, presents on the critical need for industry-wide collaboration to advance 400G technology, emphasizing cooperation among connector manufacturers, cable vendors, silicon vendors, optical vendors, and system providers. He explains that 400G's challenging initial conditions require precise link training protocols, standardized error correction methodologies, and robust Ethernet standards to ensure interoperability and reliable connections across all industry participants.

Halil Cirit, AI & HPC Systems and Services Architect at Meta, explains how hyperscalers serve as end customers driving next-generation interconnect standardization by articulating technology requirements early in the development process rather than relying on off-the-shelf solutions. He highlights the success of this collaborative initiative over the past year and encourages industry partners to join in developing optimized interconnect specifications that deliver performance advantages and meet custom design needs.

Hani Daou, Business Development Manager at Multilane, presents on behalf of the Ethernet Alliance at the Technology Exploration Forum, discussing how Ethernet remains the preferred choice for scale-up and scale-out AI applications amid unprecedented demand for network connectivity, semiconductors, and testing. He emphasizes the forum's role as a critical venue for identifying technologies that must integrate seamlessly to address interoperability challenges and meet the demanding requirements of cloud service providers and end users with their growing appetite for AI-based applications.

Nathan Tracy, President of the OIF and representative from TE Connectivity, announces the publication of OIF's 448 gigabit framework document at the Ethernet Alliance's TEF 2025, marking the first deliverable from the project launched in August 2024. The framework establishes a common industry language for addressing challenges at 448 gigabit per second data rates, including modulation selection, reach requirements, AI fabric reliability demands, and the integration of electrical and optical modulation approaches.

Cathy Liu, SerDes Architect at OIF, presents the newly published CEI-448G framework, a collaborative achievement by OIF members across AI hyperscalers, system vendors, and component manufacturers that establishes common guidelines for next-generation AI interconnect networks. The framework serves as foundational work identifying future projects including CEI-448G XSR, VSR, and LR variants, while emphasizing the need for collaboration among standards bodies such as IEEE 802.3 Ethernet, OCP, SNIA, and UEC.

Kent Lusted, Distinguished Architect at Synopsys, discusses next generation Ethernet for AI at TEF, highlighting his role as champion for an IEEE 802.3 project focused on 400 gig electrical and optical signaling for AI networks optimized for radix scale-out use cases. He emphasizes the need for collaboration among hyperscalers, standards organizations like OIF, UEC, and SNIA, and component suppliers to address three major challenges for 448 and 400 gig Ethernet: faster time to market, optimal use of available information and materials, and recognition of AI's impact on daily life through search, recommendations, pattern recognition, and infrastructure.

Ashika Pandankeril Shaji, Manager System Architect at TE Connectivity, discusses the rapid evolution of Ethernet technology to 400 Gig speeds driven by AI network bandwidth demands and the significant technical challenges this transition presents, including shrinking channel budgets and increased sensitivity to impairments. She highlights how TE Connectivity addresses these challenges through advanced modulation techniques and improved connector designs, while emphasizing the value of industry collaboration at the TIP conference to solve complex engineering problems shaping the future of Ethernet and AI networks.