2026 Showcase

2026 AI Infra Summit


Welcome to our AI Infra Summit 2026 Video Showcase! The conference, organized by Kisaco Research, brought roughly 8,000 attendees to the Santa Clara Convention Center, September 15–17, for a full-stack view of AI infrastructure — chips, interconnects, networking, memory, storage, power, and the data centers that tie them together.
We were on site filming interviews with the executives and companies below. Videos are in production and will appear here as they are published, so check back often. Meanwhile, grab our latest research brief right from this page.
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Analysis by AvidThink

What we learned at AI Infra Summit 2026

Interviews from the Santa Clara show floor converge on one constraint: power is fixed, so every layer of the stack is judged by the tokens it extracts from each watt.

  1. Tokens per watt is the new scoreboard

    Aegis tracks power compute effectiveness, Phononic controls heat at the die, Axiado claims 10–30% more tokens per watt from idle XPU and CPU cycles, and Rebellions builds 4-kilowatt inference servers. Many vendors squeezing more out of constrained power.

  2. The network decides how much of the GPU you get

    Marvell puts AI cluster efficiency at only 25–50% and calls connectivity the primary bottleneck. DriveNets links data centers past single-site power ceilings, Cornelis moves compute into NICs and switches, and Credo cuts optical fabric bring-up from 4–6 weeks to about one.

  3. Optics moves toward the silicon

    Ayar Labs has raised $650M+ for co-packaged optics; Broadcom's OCI carries 200 Gbps as multiple 50 Gbps wavelengths on one fiber; Lightmatter halves fiber count with bidirectional optics; iPronics delivers optical switching at 10–20x MEMS density.

  4. Scale-up is no longer one vendor's domain

    UALink showed working models from Cadence, NetForward, and Synopsys, with 3.0 in progress. The OCP ESUN initiative, seeded by Broadcom, has 75 members and a 1.0 spec. Even NVIDIA opens up: NVLink Fusion brings d-Matrix's Raptor XPU into its racks.

  5. Inference drives innovation — in memory and beyond

    NVIDIA shows Vera Rubin at 67x Blackwell on the AgentX benchmark. To feed agentic workloads, Marvell proposes optically connected shared memory for KV cache, Astera Labs puts memory controllers on the fabric, Penguin's CXL cards enable an 11TB server, and d-Matrix stacks DRAM on compute.

  6. Beyond the hyperscaler: control, diversity, and cost

    Nutanix sends only 10–20% of workloads to frontier models, keeping the rest on open models it controls at lower cost. DriveNets sees AMD's Helios running alongside NVIDIA, and Qualcomm scales from milliwatts to gigawatts. Buyers want choice, not lock-in.

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Highlights from industry thought leaders

Video interviews

Aegis

AI Cooling Tech Evolution

  • Every watt a GPU draws creates a matching thermal obligation, so power and cooling have to be solved as one problem as AI compute density climbs.
  • Cooling is moving from air to single-phase and two-phase direct-to-chip, which works only when the system is engineered as a whole rather than assembled from standalone components.
  • Power compute effectiveness is the metric that matters — the share of each watt that reaches the GPU rather than the supporting infrastructure.
Abstract
Jeff Moore, VP of Strategic Partnerships at Aegis, participates on a panel at AI Infra in Santa Clara discussing thermal and power challenges created by high-wattage AI compute GPUs, which are driving the evolution from air cooling to advanced direct-to-chip cooling solutions. He emphasizes power compute effectiveness as a critical metric for maximizing GPU watt allocation and highlights the industry's long-term commitment to solving these infrastructure challenges.
Arteris

Performance at Scale, Energy Efficiency & Cybersecurity

  • Performance at scale dominates the summit conversation, spanning compute, data centers, edge, and physical AI, with chiplet architectures drawing the most excitement.
  • Energy efficiency has to be architected from the silicon up through racks to the whole data center, not bolted on afterwards.
  • The attack surface has widened since Spectre and Meltdown to CPUs, NPUs, XPUs and whole semiconductor subsystems, so security must run from silicon through firmware to software.
Abstract
Michal Siwinski, Executive Vice President, Chief Product and Marketing Officer, and GM of Security Solutions at Arteris, identifies three key themes at the AI Infrastructure Summit: performance at scale across compute and data centers with emphasis on chiplet architectures, energy efficiency from silicon to data center level, and comprehensive cybersecurity integration. Siwinski notes that the attack surface has expanded significantly since the Intel Spectre and Meltdown vulnerabilities, requiring Arteris to partner with clients on security solutions spanning semiconductors through entire systems.
Astera Labs

Astera Labs Taurus 200G Smart Signal Conditioners

  • Taurus 200G-per-lane signal conditioners cover Ethernet, UALink, and PCIe in the industry's first OCP-compatible footprint spanning both retimers and redrivers.
  • Smart swap lets customers switch between retimer and redriver at any point in the design cycle, with one Cosmos software stack across both.
  • The Taurus 4 3.2T retimer and redriver were shown driving PRBS patterns across a backplane mockup, trading reach against power for scale-up links.
Abstract
Aanchal Sharma, Senior Director of Product Management at Astera Labs, introduces the company's Taurus 200 gig per lane smart signal conditioners featuring an innovative "smart swap" capability that enables customers to interchange between retimers and redrivers at any design cycle stage using a single Cosmos software stack. The demonstration showcases the Taurus 4 3.2T retimer and redriver in a backplane connection mockup for scale-up applications across Ethernet, UALink, and PCIe, with both products offering integrated telemetry and diagnostics in an OCP-compatible footprint.
Astera Labs

Smart Memory Controllers for AI Infrastructure

  • Three new LEO family members land at AI Infra 2026: the fabric-attached LEO X series, plus LEO 2 E and P series for expansion and pooling.
  • LEO X scales memory controllers alongside GPUs to add KV cache to the fabric, pairing with the Scorpio 2 320-lane switch for faster time to first token.
  • LEO 2 CXL PCIe 6 hangs 12 DDR4 DIMMs at 3DPC or 8 DDR5 at 2DPC off one controller — double the bandwidth and capacity for cloud compute, KV cache, and in-memory databases.
Abstract
Thad Omura, SVP and GM of the Compute Connectivity Group at Astera Labs, introduces three new LEO smart memory controller family members at AI Infra 2026, including the LEO X series for direct fabric-attached memory controllers and the LEO 2 E and P series for expansion and pooling applications. The LEO X series enables cohesive memory controller scaling alongside GPUs for KV cache expansion using Astera Labs' Scorpio 2 switch, while the LEO 2 CXL PCIe 6 solutions support up to 12 DDR4 or 8 DDR5 DIMMs for cloud compute, KV cache, and in-memory database workloads.
Axiado

Power Efficiency: 10-30% More Performance Per Watt

  • With 160 neoclouds starting up globally, the pitch is to optimize the power a data center already has rather than build more generation capacity.
  • The management layer boots first on the platform, collects forensic telemetry on every component, and load-balances the idle periods in XPU and CPU operation.
  • Treating racks and pods as single units with no human intervention is claimed to yield 10–30% more tokens per dollar or per watt than cooling-only approaches.
Abstract
Gopi Reddy Sirineni, President and CEO of Axiado, presents his company's intelligent platform management solution that addresses power efficiency challenges in AI data centers by monitoring system components, identifying idle periods in XPU and CPU operations, and performing automated load balancing across infrastructure. Axiado operates as a foundational management layer that boots first on platforms and enables racks and pods to function as single units, delivering 10 to 30% more tokens per dollar or per watt compared to traditional optimization methods.
Ayar Labs

Scaling Beyond Power Constraints with CPO

  • Co-packaged optics is Ayar Labs' answer to rising token demand under hard power constraints, backed by more than $650M raised this year.
  • The ecosystem on show spans TSMC silicon photonics wafers, multi-chip packages with Alchip and GUC, external laser sources, and fiber connectors from Broadcom, Foscy, and Senko.
  • Multi-source supply is the precondition for high-volume production, with Wiwynn as strategic partner and investor for hyperscale deployment.
Abstract
Vishal Chandrasekar, Director of Product Management at Ayar Labs, discusses how co-packaged optics addresses AI token generation demands amid power constraints, noting the company raised over $650 million and hosted a CPO summit on scale-up solutions and the OCI MSA. He showcases Ayar Labs' ecosystem including optical engines on TSMC's silicon photonics platform, multi-chip packages with partners like Alchip and GUC, external laser sources, fiber connectors from Broadcom, Foscy, and Senko, plus strategic partner Wiwynn for hyperscale data center deployment.
Azul

Making AI Work with Enterprise Systems

  • The hard part of enterprise AI sits downstream of the model — connecting agentic workflows to the systems that already run the business.
  • Azul's Java enterprise platform is that bridge, letting major global brands pull data and knowledge out of existing infrastructure into AI workflows.
  • Sellers' background in 3D graphics silicon frames today's GPU build-out as a familiar hardware cycle with a new integration problem attached.
Abstract
Scott Sellers, CEO of Azul, discusses how his company addresses the downstream impact of AI adoption by providing a Java enterprise platform that helps major global brands integrate AI capabilities and agentic workflows with their existing infrastructure. Drawing on his hardware industry background in graphics chips, Sellers explains how Azul enables organizations to connect AI innovations with current systems to extract data and knowledge, making AI practical for enterprises worldwide.
Broadcom

Scaling AI GPU Clusters with Ethernet

  • Ethernet now spans scale-up, scale-out, and scale-across, with the scale-up networking initiative at 75 members and a 1.0 specification published.
  • Tomahawk Ultra is in production at multiple hyperscalers at 250ns latency and 77 billion packets per second; Tomahawk 6, the first 100TB switch in volume, enables 128,000-GPU clusters in two tiers.
  • Thor Ultra is the first 800G NIC in production, supporting UAC and — through work with Microsoft and NVIDIA — MRC.
Abstract
Hasan Siraj, VP of Product Management in the Core Switching Group at Broadcom, presents on scaling AI infrastructure through Ethernet technology, highlighting the Tomahawk Ultra's production deployment at hyperscalers and the Tomahawk 6 enabling 128,000 GPU clusters. He announces Thor Ultra, the industry's first 800 gigabit NIC in production supporting both UAC and MRC through collaboration with Microsoft and NVIDIA, demonstrating Broadcom's comprehensive portfolio for AI infrastructure with an open ecosystem approach.
Broadcom

Explaining Open Compute Interconnect (OCI)

  • OCI replaces copper SerDes with an optical equivalent, using fiber's multi-wavelength capacity instead of ever-faster electrical lanes.
  • Gen 1 carries eight wavelengths per fiber — four each way — dropping the required line rate from 200 Gbps to 50 Gbps while running bidirectionally on a single fiber.
  • 50 Gbps NRZ is the energy-efficiency sweet spot, and Broadcom expects to reveal OCI-based hardware later this year.
Abstract
Near Margalit, VP and GM, Optical Systems Division at Broadcom, discusses the company's progress with OCI (Optical Connectivity Interface) technology, which uses fiber optics with multi-wavelengths to reduce speeds and power consumption by implementing eight wavelengths per fiber that lower line rates from 200 Gbps to 50 Gbps. Margalit announces that Broadcom expects to reveal OCI-based hardware later this year, positioning it as a serdes-based technology that replaces traditional copper serdes with optical solutions optimized for energy efficiency.
Clockwork.io

Suresh Vasudevan, Clockwork.io (coming soon)

Suresh Vasudevan, CEO of Clockwork.io (joined by Together AI), sat down with us at AI Infra Summit 2026. Video in production — check back soon.
Cognichip

Cognichip's AI Cuts Chip Design Time

  • Cognichip's artificial chip intelligence platform aims to compress chip development from years to weeks.
  • Physics-informed foundation models underpin AI-native workflows running from specification to formally verified RTL with zero-touch UVM verification.
  • Subsecond PPA optimization across hundreds of implementation points makes designs Pareto-aware; an idea-to-FPGA demo for the Altera ecosystem cut 20-plus weeks to days.
Abstract
Stelios Diamantidis, Chief Product Officer at Cognichip, introduces the company's AI artificial chip intelligence (ACI) enterprise solution that compresses chip development from years to weeks through physics-informed foundation models, AI-native workflows, and subsecond PPA optimization across hundreds of implementation points. The full-stack intelligence infrastructure demonstrates a complete idea-to-FPGA system for the Altera ecosystem that reduces engineering efforts from over 20 weeks to just a few days.
Cornelis Networks

Cornelis Unveils Active Compute Fabric for AI

  • The second-generation CN6000 applies Ethernet and Ultra Ethernet standards to Cornelis' native architecture, giving AI system builders interoperability.
  • A third-generation roadmap extends the company's scale-out heritage into scale-up switching via UALink and EON, targeting new accelerators, GPUs, and XPUs.
  • The active compute fabric moves compute into NICs and switches, turning the network from a passive packet-forwarding layer into an intelligent one.
Abstract
Lisa Spelman, CEO of Cornelis Networks, announces the company's second-generation CN6000 product featuring Ethernet and Ultra Ethernet standards for AI system interoperability, along with a third-generation roadmap incorporating UALink and EON for scale-up switching. She introduces the active compute fabric concept, which adds compute capabilities directly into NICs and switches to create an intelligent network that accelerates AI functions and maximizes compute efficiency beyond traditional packet-forwarding.
Credo

Credo's 1.6T AEC with 200G SerDes Powers 288-GPU Cluster

  • Credo's first 1.6T-to-1.6T active electrical cable is built on the company's first 200G SerDes, with thin cables reaching up to 6 meters plus Y cables with two 800G ends.
  • PILOT software captures runtime telemetry — FEC rate, histograms, temperature, and SNR — from both the host and remote ends of every cable.
  • A GB200 NVL72 deployment wires 288 GPUs across four racks plus a network rack with Credo's 6-meter cables to build a zero-flap scale-out fabric.
Abstract
Ameet Suri from Credo presents the company's first 1.6T-to-1.6T cable featuring 200 gig SerDes technology and advanced telemetry capabilities that capture runtime data including FEC rate, histogram, temperature, and SNR from both host and remote sides. The demonstration showcases deployment in an NVIDIA GB200 NVL72 rack configuration connecting 288 GPUs across four racks using Credo's 6-meter cables, delivering zero-flap performance and superior reliability for data center scale-out infrastructure.
Credo

Credo's 1.6T ZeroFlap Optics

  • Credo's 1.6T ZeroFlap optics extend its ecosystem with far higher reliability than commodity optics, plus built-in telemetry and inband communication.
  • The optics flag the one to two percent of problem links at installation and raise intelligent service tickets, removing the need for fiber plant characterization and manual cleaning.
  • Optical fabric bring-up drops from four to six weeks to about one week, with the Rubin-generation parts ramping for most customers in 2027.
Abstract
Don Barnetson, SVP & Head of Product at Credo, introduces the company's new 1.6 terabit ZeroFlap optics at AI Infra Summit 2026, featuring enhanced reliability, advanced telemetry, and inband communication capabilities that immediately identify problematic links upon installation. The technology reduces optical fabric deployment time from four to six weeks down to approximately one week by eliminating manual fiber plant characterization and cleaning processes, with customer ramping scheduled to begin in 2027.
Credo

Credo's ZeroFlap Optics: Proactive Link Monitoring

  • A live 51T switch cluster with ConnectX-8 NICs streams optic telemetry across 64 ports, rolled up into a single green, yellow, or red link score.
  • The link score combines pre-FEC bit error rate, multipath interference (a telltale of dust), and signal-to-noise ratio.
  • For neocloud bare-metal GPU fleets, telemetry is carried inband to the switch, alerts fire only on change with recommended actions, and optics pull themselves out of service before they start flapping.
Abstract
Don Barnetson, SVP & Head of Product at Credo, demonstrates the company's ZeroFlap optics ecosystem featuring live telemetry from a 51T switch cluster that monitors 64 ports and simplifies complex metrics into actionable green, yellow, and red indicators while tracking pre-FEC bit error rate, multipath interference, and signal-to-noise ratio. The solution addresses bare metal GPU deployments by bringing remote optic telemetry inband to the switch management point, proactively removing unstable optics from service and generating event-based alerts with recommended actions to prevent network reconvergence issues that can send billions of packets across the infrastructure.
d-Matrix

d-Matrix's 3D Stacked XPU & NVIDIA Partnership

  • d-Matrix builds silicon, subsystems, and software for ultra-low-latency inference; two acquisitions in its first year reflect that the product is now the rack, not the chip.
  • The Raptor XPU is the first 3D stacked DRAM-based XPU, co-packaging DRAM directly on compute.
  • An NVIDIA NVLink Fusion partnership puts Raptor inside NVIDIA's rack ecosystem, letting 144 XPUs communicate in one large scale-up domain.
Abstract
Sid Sheth, Founder & CEO of d-Matrix, discusses how his inference computing company builds silicon, subsystems, and software for ultra-low latency computing, completing two acquisitions in its first year to scale systems and software expertise. He highlights d-Matrix's partnership with NVIDIA to embed its Raptor XPU—the world's first 3D stacked DRAM-based XPU with co-packaged DRAM on compute—into NVIDIA's rack ecosystem, enabling 144 Raptor XPUs to communicate in large-scale domain racks as AI interconnects become critical for scaling workloads.
DriveNets

AI Infrastructure Beyond GPUs: Networking Scale & Multi-Vendor Challenges

  • Idle GPUs are the most expensive wasted resource, making the network that feeds them as critical as the accelerators themselves.
  • Scale-across networking links multiple data centers so AI clusters can keep growing past a single facility's power ceiling — already deployed in the field.
  • Multi-vendor GPU environments, with NVIDIA alongside AMD's Helios, need networking tuned to heterogeneous traffic patterns, especially for inference.
Abstract
Dudy Cohen, VP of Product Marketing at DriveNets, discusses how AI infrastructure requires robust networking to prevent expensive GPU idle time, highlighting the company's focus on scale-across capabilities that connect multiple data centers to overcome power limitations. He emphasizes the emerging multi-vendor GPU environment where different accelerators work together, requiring specialized networking infrastructure to handle data movement between heterogeneous systems—a key area of DriveNets' current deployments and summit discussions.
iPronics

Silicon Photonics: 20x Denser Optical Switching

  • iPronics builds optical circuit switching directly into silicon photonic chips, aimed at the scale-up portion of the data center network.
  • The chip-integrated approach runs 10–20x denser than MEMS-based switching and reconfigures the network roughly 1,000 times faster.
  • A recent $125M round funds supply chain, production volume, and the qualification work needed to ship a reliable product.
Abstract
Christian Dupont, CEO of iPronics, explains how the company's silicon photonic-based optical circuit switching technology delivers 10 to 20 times greater density than traditional MEMS systems while enabling network reconfiguration approximately 1,000 times faster for data center applications. iPronics is using its recent $125 million funding round to strengthen supply chains, scale production, and complete product qualification for market delivery.
Lightmatter

Bidirectional Optics for Massive GPU Clusters

  • Passage L20 brings bidirectional optics to scale-up networks, linking giant GPU clusters with half the optical fiber.
  • Halving fiber count directly addresses an anticipated global shortage in optical fiber supply.
  • With power constrained, the optics let a gigawatt data center perform like a three-gigawatt one — the same compute and GPU count, faster tokens.
Abstract
Nick Harris, Co-Founder and CEO at Lightmatter, announces the company's bidirectional optics solution with Passage L20 that enables massive GPU clusters while using half the optical fibers, addressing anticipated global fiber shortages. The technology allows gigawatt data centers to perform like three-gigawatt facilities for AI training and inference, delivering faster tokens with the same compute and GPU count despite power constraints.
Marvell

Think Optical for Efficiency & Memory Scaling

  • As workloads shift from training to inference-heavy agentic AI, CPU-to-GPU ratios move back toward 1:1 and the traditional memory pyramid has to be broken apart.
  • Optically connected shared memory adds a tier that absorbs the exponential KV cache growth of agentic AI, pooling capacity across racks at low latency and high bandwidth.
  • Optics keeps moving closer to compute — from scale-out rack links to scale-up inside the rack, and eventually onto the die itself as electrical signal integrity and beachfront limits bite.
Abstract
Preet Virk, SVP & GM Photonic Fabric at Marvell, and Ravi Mahatme, Senior Director of Photonic Fabric at Marvell, explain how optical connectivity addresses AI data center efficiency challenges as workloads shift from training to inference-heavy applications requiring sophisticated data movement between CPUs and GPUs with changing ratios and memory hierarchies. They describe how optically connected shared memory creates a new tier for handling exponential KV cache growth in agentic AI, enabling low-latency access across clusters while optical technology moves closer to compute — from rack-level connections to scale-up architectures and potentially onto dies themselves.
Marvell

AI Infrastructure Bottleneck: Solving Connectivity at 100 Terabit Scale

  • Connectivity — not compute or memory — is the primary bottleneck, and AI cluster efficiency today runs at only 25–50%.
  • Refresh cycles have compressed from 3–4 years to 12–18 months, pushing photonic fabric and optics closer to silicon as copper runs out of reach.
  • Marvell's 100Tbps switch on 3nm with 200G SerDes backs open standards (UALink, Ethernet for AI) while staying neutral across ecosystems, NVLink Fusion included.
Abstract
Rajagopal Krishnaswamy, AVP Marketing, Cloud & AI Switching at Marvell, and Jim Carroll discuss how connectivity has become the primary bottleneck in AI infrastructure, with data center refresh cycles compressing to 12-18 months and current AI cluster efficiency at only 25-50%. Krishnaswamy explains Marvell's approach to addressing these challenges through their 100 terabit per second switch with 200 gig SerDes technology, photonic fabrics, and support for open standards like UALink and Ethernet for AI while maintaining flexibility across different ecosystems including NVLink Fusion.
NextSilicon

NextSilicon: HPC, AI & RISC-V CPU Integration

  • Eight years of platform work has production chips accelerating HPC workloads at major U.S. national laboratories.
  • The Maverick chip runs the latest open-source models, with an improved successor already in development.
  • The new Arbel RISC-V CPU completes a single platform spanning HPC acceleration, AI workloads, and agentic frameworks.
Abstract
Elad Raz, Founder and CEO at NextSilicon, represents a company that has developed an eight-year comprehensive computing platform currently running production chips at major U.S. national laboratories for HPC workload acceleration. NextSilicon offers an integrated solution spanning HPC acceleration, AI workload acceleration with their Maverick chip running latest open-source models, and the new Arbel RISC-V CPU for agentic frameworks, positioning itself as a single-platform provider for HPC, AI, and CPU workloads.
Nutanix

Open-Source: Cutting Costs and Keeping Control of Your Data

  • Open-source models are closing on closed frontier models, making near-frontier capability runnable on your own infrastructure.
  • Sovereign full-stack infrastructure gives organizations control over data access and how models operate.
  • A hybrid split — frontier models for 10–20% of workloads, open models on private infrastructure for the rest — improves both governance and tokenomics.
Abstract
Debo Dutta, Chief AI Officer at Nutanix, discusses three major trends reshaping AI: open-source models approaching frontier capabilities, sovereign full-stack infrastructure, and tokenomics optimization. He advocates for a hybrid approach where organizations use expensive frontier models for 10-20% of workloads while running most agentic work on private infrastructure with open models, achieving better governance and cost efficiency.
NVIDIA

NVIDIA's Vera Rubin Performance Leap Explained

  • Agentic AI is the most complex workload data centers have faced, requiring coordination across CPUs, GPUs, networking, and storage.
  • Vera Rubin shows 67x more performance than Blackwell on the AgentX benchmark with variable sequence lengths, with further gains expected.
  • NVLink Fusion opens NVIDIA's scale-up technology to partners such as d-Matrix, keeping the platform vertically integrated but horizontally open.
Abstract
Dion Harris, AI Infrastructure at NVIDIA, discusses how agentic AI represents the most complex workload for data centers and highlights the Vera Rubin platform's capabilities, including new features for agentic tool calling that deliver 67x performance improvements on the AgentX benchmark. He emphasizes NVIDIA's vertically integrated yet horizontally open platform approach, showcasing integration with d-Matrix through NVLink Fusion that enables partners to build on the company's scale-up technology.
Penguin Solutions

CXL Solutions for Data Centers

  • Memory scaling is the bottleneck: expanding capacity affordably while cutting the data movement that drives up power and bandwidth.
  • CXL add-in cards are the answer shipping today — and what made Penguin's own 11TB AI server possible.
  • RDMA Ethernet-connected boxes extend memory across networked servers, with silicon photonics for GPU memory scaling still ahead.
Abstract
Andy Mills, Vice President of Advanced Memory Product Development at Penguin Solutions, presents the company's three-pronged approach to solving AI infrastructure memory scaling challenges through CXL add-in cards, RDMA Ethernet-connected expansion boxes, and future silicon photonics solutions. Penguin Solutions addresses cost-effective memory expansion and reduced data movement by offering immediate CXL solutions that enable unprecedented server configurations, including their own 11 terabyte AI server product.
Phononic

Managing Heat at Die Level for Maximum GPU Output

  • Phononic applies thermal control at the die level for GPU and networking partners, rather than at the rack or the room.
  • The cooling infrastructure layers onto existing liquid cooling instead of replacing it.
  • Software control over that layer is what converts cooling headroom into more tokens per megawatt.
Abstract
Ryan Brown, Director of Product Management at Phononic, presents at the AI Infrastructure Summit on thermal control solutions that manage heat at the die level for GPU and networking partners. Phononic's cooling infrastructure integrates with existing liquid cooling systems and provides software control to maximize output and achieve more tokens per megawatt.
Qualcomm

From Milliwatts to Gigawatts Across Devices

  • Qualcomm's AI portfolio runs from doorbells to data centers — a milliwatt to a gigawatt — and it claims to be the only vendor spanning that whole range.
  • High bandwidth compute and token acceleration target sustained token generation at lower power.
  • A company built on endpoints is now scaling into rack-scale deployment and a push into physical AI, humanoid robotics included.
Abstract
Vinesh Sukumar, Vice President, Product Management at Qualcomm, presents the company's extensive AI portfolio covering devices from doorbells to data centers, spanning a power range from milliwatts to gigawatts. He discusses Qualcomm's innovations in high bandwidth compute and token acceleration, while highlighting the company's expansion from endpoint devices into rack-scale deployment and upcoming initiatives in physical AI applications including humanoid robotics.
Rebellions

Making Inferencing Affordable at Scale

  • Inferencing buyers have moved past benchmark tokens to production concerns: security, enterprise readiness, and economics.
  • Rebellions' 4-kilowatt servers cut operating expense enough to support lower-cost service tiers and push inferencing unit economics toward zero.
  • The newly released Rebel product ships alongside a partnership with AI&, an inference provider serving the Japanese market.
Abstract
Marshall Choy, CBO at Rebellions, explains how the AI inferencing industry is moving beyond performance benchmarks to focus on practical production needs like security, enterprise readiness, and economics, with Rebellions building energy-efficient 4-kilowatt servers that lower operating costs and enable affordable service tiers. He announces the Rebel product launch and a partnership with AI& to serve the Japanese market, positioning energy efficiency and cost reduction as essential for making AI inferencing accessible to organizations and applications that previously couldn't afford it.
Synopsys

Building Trust in Physical AI

  • As AI moves into drones, vehicles, and household machines, trust becomes the constraint — predictions need ±1% accuracy when the decision is life-or-death.
  • Using physics as the source of truth in synthetic data and simulation is what makes a digital twin validated rather than merely plausible.
  • A partnership with NVIDIA brings accelerated computing and agentic orchestration to pre-processing, simulation, and solving, lowering the barrier to 99% engineering accuracy.
Abstract
Anthony Matarazzo, Head of Physical AI GTM at Synopsys, discusses how trust and accuracy are critical as AI transitions from digital models to physical machines, emphasizing that physics-based synthetic data and simulation enable organizations to predict outcomes with ±1% accuracy for life-or-death decisions. He explains that Synopsys is partnering with NVIDIA to build a modernized engineering foundation using accelerated computing and agentic technologies, creating validated digital twins that help companies achieve the 99% engineering accuracy required for intelligent physical systems handling complex edge cases.
UALink Consortium
  • Three vendors showed working UALink models: Cadence linking two FPGAs directly, NetForward's FPGA-based switch, and Synopsys proving the 224G Ethernet PHY layer over cable.
  • The demonstrations run on the 1.0 specification, with 2.0 released in April and 3.0 now in progress.
  • Working IP from multiple vendors marks the shift from specification to silicon for scale-up interconnect.
Abstract
Kurtis Bowman, Board Chair of the UALink Consortium, announces significant progress with three major demonstrations of working models from IP vendors, including Cadence's FPGA devices with direct UALink connection, NetForward's switch in FPGA form, and Synopsys' board proving 224 gig Ethernet PHY layer functionality. The consortium advances at a strong pace with demonstrations based on the 1.0 specification, the 2.0 specification released in April, and the 3.0 specification now in progress.
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