d-Matrix
Executive perspectives from d-Matrix across NextGenInfra's event and research showcases.
4 video interviews · 2025–2026
d-Matrix's 3D Stacked XPU & NVIDIA Partnership
- d-Matrix builds silicon, subsystems, and software for ultra-low-latency inference; two acquisitions in its first year reflect that the product is now the rack, not the chip.
- The Raptor XPU is the first 3D stacked DRAM-based XPU, co-packaging DRAM directly on compute.
- An NVIDIA NVLink Fusion partnership puts Raptor inside NVIDIA's rack ecosystem, letting 144 XPUs communicate in one large scale-up domain.
Abstract
Sid Sheth, Founder & CEO of d-Matrix, discusses how his inference computing company builds silicon, subsystems, and software for ultra-low latency computing, completing two acquisitions in its first year to scale systems and software expertise. He highlights d-Matrix's partnership with NVIDIA to embed its Raptor XPU—the world's first 3D stacked DRAM-based XPU with co-packaged DRAM on compute—into NVIDIA's rack ecosystem, enabling 144 Raptor XPUs to communicate in large-scale domain racks as AI interconnects become critical for scaling workloads.
d-Matrix Attention Feed-Forward Disaggregation at 800+ Tokens/Sec
- d-Matrix announced Squadron, its cluster-scale solution, at the 2026 summit.
- A live attention feed-forward disaggregation (AFD) demo ran attention on NVIDIA H100 GPUs and experts on Corsair nodes, topping 800 tokens per second per user on a 20B-parameter model.
- Memory-bound expert workloads suit Corsair's memory-bandwidth-optimized design, enabling larger batches and keeping nodes efficiently utilized.
Abstract
Sree Ganesan, VP of Product at d-Matrix, announces the company's Squadron cluster-scale solution and demonstrates the industry's first live attention feed-forward disaggregation on heterogeneous compute, running a 20 billion parameter model with attention on NVIDIA H100 GPUs while experts execute on d-Matrix's Corsair nodes at over 800 tokens per second per user. The AFD approach optimizes performance by leveraging Corsair's memory bandwidth architecture for memory-bound expert workloads while keeping attention operations on GPUs, enabling higher batch processing and efficient node utilization.
d-Matrix on AI Efficiency and Scale
- d-Matrix's Jetream IO accelerator pairs with its Corsair compute accelerator for multi-node scaling.
- PCI cards support up to eight Corsair accelerators per node.
- Cross-node scaling is achieved through an Ethernet switch.
Abstract
Sid Sheth, CEO of d-Matrix, introduces their Jetream IO accelerator product that works alongside their Corsair compute accelerator to enable multi-node AI workload scaling. The solution uses PCI cards supporting up to eight Corsair accelerators per node, with the Jetream IO accelerator enabling cross-node scaling through an Ethernet switch.
OCP-Compliant AI Inference at Rack Scale
- d-Matrix showcases a rack-scale AI inference accelerator using ODSA, Bunch of Wires, and block floating-point numerics.
- New SquadRack product, built with Arista, Super Micro, and Broadcom, follows OCP Open Rack Spec V3.
- Roadmap adds support for EON, the Ethernet scale-up network.
Abstract
Max Sbabo, Senior Staff Engineer at d-Matrix, presents the company's rack scale AI inference accelerator at the OCP Summit, highlighting their collaboration with OCP through ODSA workgroups, Bunch of Wires standard implementation, and pioneering block floating-point numerics. He announces d-Matrix's SquadRack product developed with Arista, Super Micro, and Broadcom following OCP's Open Rack Specification V3 standards, along with support for the new EON (Ethernet scaleup network) on their roadmap.