Synopsys

Anthony Matarazzo, Head of Physical AI GTM at Synopsys, discusses how trust and accuracy are critical as AI transitions from digital models to physical machines, emphasizing that physics-based synthetic data and simulation enable organizations to predict outcomes with ±1% accuracy for life-or-death decisions. He explains that Synopsys is partnering with NVIDIA to build a modernized engineering foundation using accelerated computing and agentic technologies, creating validated digital twins that help companies achieve the 99% engineering accuracy required for intelligent physical systems handling complex edge cases.

Abhijeet Chakraborty, VP of Engineering at Synopsys, examines the accelerating adoption of multi-die designs for AI applications, highlighting how advanced packaging enables larger formats and better interconnect density while presenting complex engineering challenges in power delivery, thermal management, and multiphysics modeling that exceed the capabilities of traditional manual methods.

Kent Lusted, Distinguished Architect at Synopsys and chair of the IEEE 802.3dv 400 Gig per lane signaling task force, updates progress on Ethernet standards development addressing AI network demands for scale-up, scale-out, and front-end connectivity through copper interconnects, electrical backplanes, copper cables, and 500-meter optical reaches. The working group has achieved industry consensus on reusing existing logic architecture, converging toward PAM4 modulation for optical interconnects, and defining specifications for both PAM4 and PAM6 electrical standards to provide flexibility across various media types and interconnect architectures.

Kent Lusted, Distinguished Architect at Synopsys, discusses next generation Ethernet for AI at TEF, highlighting his role as champion for an IEEE 802.3 project focused on 400 gig electrical and optical signaling for AI networks optimized for radix scale-out use cases. He emphasizes the need for collaboration among hyperscalers, standards organizations like OIF, UEC, and SNIA, and component suppliers to address three major challenges for 448 and 400 gig Ethernet: faster time to market, optimal use of available information and materials, and recognition of AI's impact on daily life through search, recommendations, pattern recognition, and infrastructure.

Yervant Zorian, Fellow & Chief Architect at Synopsys, highlights the potential of cost-effective chiplets over monolithic chips, suggesting the industry is nearing the limits of electronics, thus making a shift to chiplets more likely.