Synopsys

Abhijeet Chakraborty, VP of Engineering at Synopsys, examines the accelerating adoption of multi-die designs for AI applications, highlighting how advanced packaging enables larger formats and better interconnect density while presenting complex engineering challenges in power delivery, thermal management, and multiphysics modeling that exceed the capabilities of traditional manual methods.

Kent Lusted, Distinguished Architect at Synopsys, discusses next generation Ethernet for AI at TEF, highlighting his role as champion for an IEEE 802.3 project focused on 400 gig electrical and optical signaling for AI networks optimized for radix scale-out use cases. He emphasizes the need for collaboration among hyperscalers, standards organizations like OIF, UEC, and SNIA, and component suppliers to address three major challenges for 448 and 400 gig Ethernet: faster time to market, optimal use of available information and materials, and recognition of AI's impact on daily life through search, recommendations, pattern recognition, and infrastructure.

Yervant Zorian, Fellow & Chief Architect at Synopsys, highlights the potential of cost-effective chiplets over monolithic chips, suggesting the industry is nearing the limits of electronics, thus making a shift to chiplets more likely.