SiFive
Executive perspectives from SiFive across NextGenInfra's event and research showcases.
1 video interview · 2025
RISC-V for AI
- SiFive touts RISC-V vector length agnostic instructions for consistent execution from data center to edge.
- X100 series adds scalar co-processing, hardware exponential instruction, and memory improvements.
- Claims up to 322x performance gains over previous generations.
Full summary
John Simpson, Senior Principal Architect at SiFive, showcases RISC-5's vector length agnostic instructions that enable consistent software execution across data centers and edge devices at the AI Infra Summit. He introduces SiFive's X100 series featuring scalar co-processing, hardware pipeline exponential instruction, and memory system improvements that deliver up to 322x performance gains over previous generations.